A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis

Lin, Chau-Jy; Wong, Cheng-Chi; Chang, Hsie-Chia

doi:10.1109/jssc.2013.2274883

Cited by 7 publications

(3 citation statements)

References 17 publications

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“…Compared with [25], our algorithm had obvious advantages in throughput. Although the throughput of our design was close to [26] and less than [27], the proposed LUT-Nor-Log-MAP algorithm had better decoding performance than the Max-Log-MAP algorithm [26]. Compared with [27], the logic resource consumption in our design was greatly reduced.…”

Section: Throughput =mentioning

confidence: 87%

Turbo Decoder Design based on an LUT-Normalized Log-MAP Algorithm

Wang

et al. 2019

Entropy

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Turbo codes have been widely used in wireless communication systems due to their good error correction performance. Under time division long term evolution (TD-LTE) of the 3rd generation partnership project (3GPP) wireless communication standard, a Log maximum a posteriori (Log-MAP) decoding algorithm with high complexity is usually approximated as a lookup-table Log-MAP (LUT-Log-MAP) algorithm and Max-Log-MAP algorithm, but these two algorithms have high complexity and high bit error rate, respectively. In this paper, we propose a normalized Log-MAP (Nor-Log-MAP) decoding algorithm in which the function max* is approximated by using a fixed normalized factor multiplied by the max function. Combining a Nor-Log-MAP algorithm with a LUT-Log-MAP algorithm creates a new kind of LUT-Nor-Log-MAP algorithm. Compared with the LUT-Log-MAP algorithm, the decoding performance of the LUT-Nor-Log-MAP algorithm is close to that of the LUT-Log-MAP algorithm. Based on the decoding method of the Nor-Log-MAP algorithm, we also put forward a normalization functional unit (NFU) for a soft-input soft-output (SISO) decoder computing unit. The simulation results show that the LUT-Nor-Log-MAP algorithm can save about 2.1% of logic resources compared with the LUT-Log-MAP algorithm. Compared with the Max-Log-MAP algorithm, the LUT-Nor-Log-MAP algorithm shows a gain of 0.25~0.5 dB in decoding performance. Using the Cyclone IV platform, the designed Turbo decoder can achieve a throughput of 36 Mbit/s under a maximum clock frequency of 44 MHz.

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Section: Throughput =mentioning

confidence: 87%

Turbo Decoder Design based on an LUT-Normalized Log-MAP Algorithm

Wang

et al. 2019

Entropy

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“…The following discussion serves to a comparison of VLSI implementation with related works in terms of configurability and efficiency. It is noted that all the references except [32] support LTE/LTE-Advanced standard. In addition, multi-standard is supported in [31] with HSPA þ/LTE and in [33] with LTE/WiMAX/DVB-RCS.…”

Section: Comparison Analysismentioning

confidence: 99%

“…This work TCAS-I 2014 [29] TCAS-I 2014 [30] TCAS-I 2014 [31] JSSC 2013 [32] DATE 2013 [33] ISTC 2012 [15] Integration 2011 [18] JSSC 2011 [22] Standard ( …”

Section: Referencementioning

confidence: 99%

High performance parallel turbo decoder with configurable interleaving network for LTE application

Yan

et al. 2016

Integration

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A 188-Length Full Code Rate 333Mbps 1.08mm² Radix-4 Hybrid-Trellis Turbo Decoder with Zero Patching for 3GPP LTE-A

Chang

Lin

Sun

et al. 2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis

Cited by 7 publications

References 17 publications

Turbo Decoder Design based on an LUT-Normalized Log-MAP Algorithm

Turbo Decoder Design based on an LUT-Normalized Log-MAP Algorithm

High performance parallel turbo decoder with configurable interleaving network for LTE application

A 188-Length Full Code Rate 333Mbps 1.08mm² Radix-4 Hybrid-Trellis Turbo Decoder with Zero Patching for 3GPP LTE-A

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A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis

Cited by 7 publications

References 17 publications

Turbo Decoder Design based on an LUT-Normalized Log-MAP Algorithm

Turbo Decoder Design based on an LUT-Normalized Log-MAP Algorithm

High performance parallel turbo decoder with configurable interleaving network for LTE application

A 188-Length Full Code Rate 333Mbps 1.08mm2 Radix-4 Hybrid-Trellis Turbo Decoder with Zero Patching for 3GPP LTE-A

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Product

Resources

About

A 188-Length Full Code Rate 333Mbps 1.08mm² Radix-4 Hybrid-Trellis Turbo Decoder with Zero Patching for 3GPP LTE-A