A 40 MHz 64-bit floating-point co-processor

Molnar, K.J.; Ho, Chung-Yih; Staver, Daniel A.; Davis, Brian; Jerdonek, R.T.

doi:10.1109/isscc.1989.48228

Cited by 7 publications

(1 citation statement)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These tools have been used to compile several different ASK designs that were reported in [18] and {19], and as a chip integrator for a custom IC design project [20].…”

Section: Application Tool Developmentmentioning

confidence: 99%

FACE core environment: the model and its application in CAE/CAD tool development

Smith¹,

Duff²,

Dragomirecky³

et al. 1989

Proceedings of the 1989 26th ACM/IEEE Conference on Design Automation Conference - DAC '89

View full text Add to dashboard Cite

Many aspects of design automation software have similar requirements for representing, manipulating, and storing design information.The recognition of these common requirements in CAD tools, allows the Flexible Architecture Compilation Environment's (FACE) Core Environment to provide a suite of high level tools for the CAD developer. The Core Environment software has been developed using object-oriented software technology, and may be readily adapted to specific applications.The focus of the core environment is to improve the productivity of CAD tool developers through better tool integration and a stateof-the-art software development environment.This Core Environment software has been used in the development of an integrated tool set covering algorithm specification, structural synthesis, and physical assembly of digital hardware systems. The focus of this paper is on the Core Environment's organization and its use in application tool development. IntroductionThe development of the Flexible Architecture Compilation Environment (FACE) Core Environment was motivated by the observation that many diverse application tools have similar requirements for representing and manipulating design information. These application tools typically represent engineering data using graph and hypergraph (i.e., network) data structures [l] and exploit similar techniques for manipulating and analyzing this information. The challenge in developing the CAD environment is to exploit the commonality among the various application tools while accommodating the need for customization. The Core Environment provides (i) a formal model for representing graph and hypergraph data structures, (ii) common graph algorithms that operate on this model, (iii) higher level application development tools such as an interactive editor, a data query language, persistent data storage and retrieval, and design configuration management, and (iv) the integration framework with a consistent user interface for delivering application tools to the end user.After a brief discussion on the motivation for this work and related work, this paper describes the underlying data models, algorithms and tools provided by the Core Environment. Use of this core object set is illustrated by (i) examining the FACE data Row and hardware netlist representations, (ii) how the Core Environment has been used to rapidly prototype various CAD ~aols, and (iii) the implementation of a Design Management System.

show abstract

“…These tools have been used to compile several different ASK designs that were reported in [18] and {19], and as a chip integrator for a custom IC design project [20].…”

Section: Application Tool Developmentmentioning

confidence: 99%

FACE core environment: the model and its application in CAE/CAD tool development

Smith¹,

Duff²,

Dragomirecky³

et al. 1989

Proceedings of the 1989 26th ACM/IEEE Conference on Design Automation Conference - DAC '89

View full text Add to dashboard Cite

show abstract

Leading-zero anticipatory logic for high-speed floating point addition

Suzuki

Morinaka

Makino

et al. 1996

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

An area model for on-chip memories and its application

Mulder

Quach

Flynn

1991

IEEE J. Solid-State Circuits

165

View full text Add to dashboard Cite

Absfrud --In the implementation of a processor, it is often necessary to abstract cost constraints into architecture measures for making trade-offs. An important cost measure for an on-chip memory is its occupied silicon area. Since the performance of an on-chip memory is characterized by size (storage capacity), a mapping from size to area is needed. Simple models have been proposed in the past for such a purpose. These models, however, are of unproven validity and only apply when comparing relatively large buffers ( > 128 words for caches, > 32 words for register sets) of the same structure (e.g., cache versus cache).In this paper we present an area model for on-chip memories. The area model considers the supplied bandwidth of a memory cell and includes such buffer overhead as control logic, driver logic, and tag storage, thereby permitting comparison of data buffers of different structures and arbitrary sizes. The model gave less than 10% error when verified against real caches and register files. We then show that comparing cache performance as a function of area, rather than size, leads to a significantly different set of organizational trade-offs.

show abstract

A 40 MHz 64-bit floating-point co-processor

Cited by 7 publications

References 1 publication

FACE core environment: the model and its application in CAE/CAD tool development

FACE core environment: the model and its application in CAE/CAD tool development

Leading-zero anticipatory logic for high-speed floating point addition

An area model for on-chip memories and its application

Contact Info

Product

Resources

About