A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS Technology

Usama, Muhammad; Kwaśniewski, T.

doi:10.1109/iscas.2007.378051

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Cited by 7 publications

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“…Afterwards, as the technology nodes went below 1 µm, it was possible to design multi-gigahertz speed frequency dividers in CMOS. The architectures of these CMOS dividers were commonly based on limited-outputswing current-mode-logic (CML) or LC injection-lock topologies [4]- [7].…”

Section: Introductionmentioning

confidence: 99%

Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology

Özsema

Kostak

Demirci

et al. 2015

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP &Amp; International Symposium on System-on-Chip (SoC)

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Abstract-In this paper we present the design of a programmable frequency divider in 28 nm FD-SOI CMOS technology. It consists of the cascade of a divide-by-2 cell and divideby-2/3 blocks. The final circuit is capable of dividing by even numbers between 128 and 254. The forward-body-bias property of the process and the differential-cascode voltage-switch-logic (DCVSL) family are used to achieve high operation speed. The proposed circuit achieves a maximum operating frequency of 20 GHz at 1 V supply voltage. And the area and the power consumption of the programmable divider are 1815 µm 2 and 4.35 mW, respectively.

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Section: Introductionmentioning

confidence: 99%