A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology

Navid, Reza; Chen, E-Hung; Hossain, Masum; Leibowitz, Brian; Ren, Jihong; Chou, Chuen-huei Adam; Daly, Barry; Aleksic, Milivoje; Su, Bruce; Li, Simon; Shirasgaonkar, Makarand; Heaton, Fred; Zerbe, J.; Eble, John

doi:10.1109/jssc.2014.2374176

Cited by 70 publications

(11 citation statements)

References 16 publications

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“…The bandwidth can further be increased by using stronger drivers at the cost of higher energy per bit. [24] 40 [37] Energy .48 [24] 23.2 [37] Max Bandwidth per mm (Gbps/mm) …”

Section: Superchips Benefitsmentioning

confidence: 99%

Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme

Jangam

Pal

Bajwa

et al. 2017

2017 IEEE 67th Electronic Components and Technology Conference (ECTC)

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Abstract-In this paper, we describe the performance and power benefits of our Fine Pitch integration scheme on a Silicon Interconnect Fabric (Si IF). Here we propose a Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet to interconnect fabric assembly. We show the dramatic improvements in bandwidth, latency, and power are achievable through our integration scheme where small dielets (1-25 mm 2 ) are attached to a rigid Silicon Interconnect Fabric (Si-IF) at fine interconnect pitch (2-10 μm) and short inter-die distance (50-500 μm) using solderless metal-to-metal thermal compression bonding (TCB). Our simulations show that links in the Si-IF with short wire-lengths (<500 μm) have excellent signal transfer characteristics with low channel loss (<-2 dB) and low cross-talk (<-15 dB). With fine interconnect pitches (<10 μm), our scheme can achieve >5-25x improvement in data bandwidth. This can improve system performance (>20x) when compared to PCB-style integration and may even approach single die SoC metrics in some cases. Furthermore our protocol is simple and non-proprietary. We show that this scheme enables heterogeneous system integration using a dielet based assembly method and provides significant reduction in design and validation cost.System-level analysis of heterogeneous integration scheme promises power benefits of more than 15% even for very small systems.

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“…The bandwidth can further be increased by using stronger drivers at the cost of higher energy per bit. [24] 40 [37] Energy .48 [24] 23.2 [37] Max Bandwidth per mm (Gbps/mm) …”

Section: Superchips Benefitsmentioning

confidence: 99%

Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme

Jangam

Pal

Bajwa

et al. 2017

2017 IEEE 67th Electronic Components and Technology Conference (ECTC)

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“…The structure of DFE equalizer is simple and easy to operate at relatively high rate. [11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

A 20 Gb/s Wireline Receiver with Adaptive CTLE and Half-Rate DFE in 0.13 µm Technology

Zhang

Zhan

2017

Lecture Notes in Computer Science

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This paper presents a 20 Gb/s receive equalizer including an adaptive continuous time linear equalizer (CTLE) and a 2-tap half-rate decision feedback equalizer (DFE) in 0.13 µm BiCMOS technology for high speed serial link. The CTLE can adjust the ratio of high frequency and low frequency components adaptively by detecting the energy at both ends of a slicer and then generating a control signal by an integrator. Following the CTLE is a half-rate DFE which can get a better trade-off between the working speed and design complexity especially for the case of 20 Gb/s or above. The chip area including pads and chipguarding is about 0.72×0.86 mm 2 and the power consumption is about 528 mW. Post simulation results show that the horizontal eye opening of the equalized data can be up to 0.9 UI at 20 Gb/s.

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“…As a result, the required bandwidth of I/O transceivers supporting routers and server systems should be greatly improved in order to satisfy the increased demand. Nowadays, the per-pin bandwidth of the serial link transceivers fabricated in CMOS technology has reached 40 Gb/s in several reported designs [2]- [6]. The energy efficiency of the serial link transceiver is another important factor.…”

Section: Introductionmentioning

confidence: 99%

“…The energy efficiency of the serial link transceiver is another important factor. The energy efficiency is 90 pJ/bit in the first 40 Gb/s transceiver reported in [6] and has been improved to 23.2 pJ/bit in a recent design reported in [2]. However, there is still plenty of room for improvement, and therefore, circuits and architectures to improve energy efficiency are being continuously explored.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

Bae

Park

et al. 2016

IEEE J. Solid-State Circuits

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This paper describes the design of a 10 GHz phase-locked loop (PLL) for a 40 Gb/s serial link transmitter (TX). A two-stage ring oscillator is used to provide a four-phase, 10 GHz clock for a quarter-rate TX. Several analyses and verification techniques, ranging from the clocking architectures for a 40 Gb/s TX to oscillation failures in a two-stage ring oscillator, are addressed in this paper. A tri-state-inverterbased frequency-divider and an AC-coupled clock-buffer are used for high-speed operations with minimal power and area overheads. The proposed 10 GHz PLL fabricated in the 65 nm CMOS technology occupies an active area of 0.009 mm 2 with an integrated-RMS-jitter of 414 fs from 10 kHz to 100 MHz while consuming 7.6 mW from a 1.2-V supply. The resulting figure-ofmerit is -238.8 dB, which surpasses that of the state-of-the-art ring-PLLs by 4 dB. Index Terms-CMOS, jitter, phase-locked loop (PLL), ring oscillator, serial link transmitter.

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A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology

Cited by 70 publications

References 16 publications

Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme

Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme

A 20 Gb/s Wireline Receiver with Adaptive CTLE and Half-Rate DFE in 0.13 µm Technology

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

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