A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS

A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS

“…Recent works have demonstrated that source-series terminated (SST) PAM-4 drivers exhibit good linearity due to their voltage operation mode which does not involve current mismatch [21,22,23]. Unfortunately, the output impedance matching and tunable adjustment for the feed-forward equalizer (FFE) result in heavy self-drain loads, requesting an advanced process to support a high operation speed [24,25,26]. In contrast, the current mode logic (CML) PAM-4 drivers can fully exploit the process potentials as their compact NMOS driving topology naturally features fast current switching speed and small parasitic capacitance [27].…”

A 16.7-Gb/s full-transition avoidance PAM-4 2-tap FFE transmitter with shunt switches for display interfaces

“…However, the channel bandwidths of such display systems are severely limited due to loss and reflections from long PCB traces and FPC (Flexible Printed Circuit) structures. Therefore, transceivers for the display interfaces should adopt advanced signaling (such as PAM-4 [4][5][6][7]) and equalization (such as FFE [8,9]) techniques to achieve such high data rates in energy-efficient ways. However, the voltage mode FFE driver suffers from high power consumption, and the PAM-4 signaling yields high sensitivity to residual ISIs.…”

“…4(a) shows the structure of the proposed output driver slice with a shunt switch. Compared with previous PAM-4 transmitters [6,7], the design avoids the use of current-mode branches to fully take advantage of voltage-mode drivers in terms of energy efficiency. The driver is divided into 12 slices, and each slice is composed of four impedance-controlled pull-up/down switches and one shunt switch.…”