A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery

Tang, Liangxiao; Gai, Weixin; Shi, Linqi; Xiao, Xiangheng

doi:10.1109/iscas.2017.8050226

Cited by 3 publications

(2 citation statements)

References 6 publications

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“…Additionally this also means that more edge information is available to the CDR circuit such that a higher performance can be achieved. It should be noted that there is already one publication [26] which uses all three thresholds without 2-level transition elimination. Below we will also discuss the solution of [26] and compare it to other edge detection schemes.…”

Section: Introductionmentioning

confidence: 99%

“…It should be noted that there is already one publication [26] which uses all three thresholds without 2-level transition elimination. Below we will also discuss the solution of [26] and compare it to other edge detection schemes. The analysis will also show that a phase detector which uses all three thresholds has a better performance compared to its one threshold alternative.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

The Truth About 2-Level Transition Elimination in Bang-Bang PAM-4 CDRs

Verbeke

Torfs

Rombouts

2021

IEEE Trans. Circuits Syst. I

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Reception of 4-level pulse amplitude modulation (PAM-4) requires a clock and data recovery (CDR) circuit, typically implemented by a PLL-like structure. An essential block in such a CDR is the phase detector which should detect whether the recovered clock leads or lags the incoming data edges. In typical implementations an incoming data edge is detected by sensing whether the incoming waveform crosses a data threshold level. However, there is some ambiguity in detecting the incoming data edge because PAM-4 modulation has 3 thresholds. If the waveform crosses multiple threshold levels, the level crossings will occur at different time instants due to the finite rise/fall time of the incoming waveform. In this work, we first analyze qualitatively and quantitatively CDR systems that use one threshold for phase adjustment. Here, eliminating the 2-level transitions decreases the amount of jitter injected by the phase detector. However, the available transitions for phase adjustment are also reduced, which lowers the CDR's robustness. Secondly, for CDR systems using three thresholds, a combination of two techniques: majority voting and elimination of 2-level transitions is investigated. We prove that in this case, the elimination of 2-level transitions is not needed and even gives a worse performance when implemented.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%