A 4 Megabit Carbon Nanotube-based nonvolatile memory (NRAM)

Rosendale, Glen; Kianian, S.; Manning, Monte; Hamilton, Darlene; Huang, Xiaoping; Robinson, K.M.; Kim, Young Weon; Rueckes, Thomas

doi:10.1109/esscirc.2010.5619747

Cited by 13 publications

(15 citation statements)

References 4 publications

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“…In detail, the cell resistance is low when the CNTs are close together and the tunneling current is high. In contrast, the cell resistance is high when the CNTs [14]. Set and reset voltage polarities are reversed.…”

Section: Characteristics Of Nram Cell Arraymentioning

confidence: 96%

“…Fig. 2 shows photograph of a 4 Mbit NRAM cell array [14]. Data is stored in the NRAM cell by changing the cell resistance.…”

Section: Characteristics Of Nram Cell Arraymentioning

confidence: 99%

“…Fig. 5 shows the architecture of the NRAM cell array [14]. The one-transistor-one-resistor memory cell structure is used.…”

Section: Characteristics Of Nram Cell Arraymentioning

confidence: 99%

“…Formula (3) is used to calculate BCH ECC decoding latency t ECC [14], [17]. In this formula, m is the number of required parity bits to recover one bit error, n is BCH ECC code length, p is the number of decoding circuits to work in parallel, f is the circuit folding factor, F is circuit operating frequency in MHz, and t is the number of ECC correctable bits.…”

Section: B Parity Overhead Reduction and Ecc Decoding Latency Reductionmentioning

confidence: 99%

“…In this paper, a novel error correction scheme, called reset-check-reverse-flag (RCRF), is proposed to improve both SCM reliability and read performance. A 4 Mbit NRAM cell array [14] is measured over 10 8 write cycles to verify the proposed scheme.…”

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confidence: 99%

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Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

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Iwasaki

Tanakamaru

et al. 2016

IEEE J. Solid-State Circuits

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A novel error correction scheme, called reset-checkreverse-flag (RCRF), is proposed to improve the reliability of storage class memories (SCMs). RCRF divides the conventional Bose-Chaudhuri-Hocquenghem (BCH) code length into multiple subsections. One flag bit is added to each subsection to correct program errors. By reversing the flag bit and user data, at least one reset error in each subsection can be recovered. A 4 Mbit carbon nanotube (CNT) based nano-random access memory (NRAM) cell array is measured to verify this scheme. During 10 8 write cycles, it is demonstrated that RCRF reduces the program bit error rate (BER) by 50% and only requires 0.4% extra array area for the flag bits. Next, BCH ECC is applied after RCRF to correct the remaining errors. Compared with the conventional BCH ECC-only approach, the proposed combination of RCRF and BCH ECC reduces parity overhead by 35% and ECC decoding latency by 16%. Therefore, RCRF is especially suited for read-intensive types of data storage, such as video and audio. On the other hand, for high endurance applications, RCRF and BCH ECC is also effective to improve the cycling reliability of resistive memories, and 50 times endurance extension is demonstrated for a 50 nm Al x O y resistive RAM (ReRAM) test chip.Index Terms-Carbon nanotube, emerging memory, error correcting code, memory controller, non-volatile memory, NRAM, reliability, solid-state drive, storage class memory.

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Section: Characteristics Of Nram Cell Arraymentioning

confidence: 96%

“…Fig. 2 shows photograph of a 4 Mbit NRAM cell array [14]. Data is stored in the NRAM cell by changing the cell resistance.…”

Section: Characteristics Of Nram Cell Arraymentioning

confidence: 99%

“…Fig. 5 shows the architecture of the NRAM cell array [14]. The one-transistor-one-resistor memory cell structure is used.…”

Section: Characteristics Of Nram Cell Arraymentioning

confidence: 99%

Section: B Parity Overhead Reduction and Ecc Decoding Latency Reductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Ning

Iwasaki

Tanakamaru

et al. 2016

IEEE J. Solid-State Circuits

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Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array

Sworna

UlHaque

Tara

et al. 2016

IET Circuits, Devices & Systems

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The binary coded decimal (BCD) system is suitable for digital communication, which can be designed by field programmable gate array (FPGA) technology, where look up table (LUT) is one of the major components of FPGA. In this study, the authors proposed a low power and area efficient LUT-based BCD adder which is constructed basically in three steps: First, a new technique is introduced for the BCD addition to obtain the correct BCD digit. Second, a new controller circuit of LUT is presented which is designed to select and send Read/Write voltage to memory cell for performing Read or Write operation. Finally, a compact BCD adder is designed using the proposed LUT. Their proposed 2-input LUT outperforms the existing best one providing 65.8% improvement in terms of area, 44.1% for Read operation and 43.5% for Write operation in power consumption. The proposed BCD adder using FPGA gains a radical achievement compared with the existing best-known LUT-based BCD adder providing prominent better performance of 65.6% in area and 48.3% less power consumption.

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Advancement of microelectronics-grade carbon nanotube materials for NRAM<sup>®</sup> device manufacture

Lamb

Gibbons

Jiang

et al. 2014

25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014)

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A 4 Megabit Carbon Nanotube-based nonvolatile memory (NRAM)

Cited by 13 publications

References 4 publications

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array

Advancement of microelectronics-grade carbon nanotube materials for NRAM<sup>®</sup> device manufacture

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A 4 Megabit Carbon Nanotube-based nonvolatile memory (NRAM)

Cited by 13 publications

References 4 publications

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array

Advancement of microelectronics-grade carbon nanotube materials for NRAM<sup>&#x00AE;</sup> device manufacture

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Advancement of microelectronics-grade carbon nanotube materials for NRAM<sup>®</sup> device manufacture