A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology

Sandre, G. De; Bettini, Luca; Pirola, Alberto; Marmonier, L; Pasotti, M.; Borghi, Massimo; Mattavelli, Paolo; Zuliani, P.; Scotti, L.; Mastracchio, G.; Bedeschi, F.; Gastaldi, R.; Bez, R.

doi:10.1109/jssc.2010.2084491

Cited by 26 publications

(10 citation statements)

References 15 publications

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“…In addition, the XRR measurements were carried out to obtain the density change rate for different thin‐film thicknesses. Finally, the 4 Mb PCRAM chips were fabricated by the 40 nm complementary metal oxide semiconductor (CMOS) process and consist of one‐transistor and one‐resistor (1T1R) PCRAM cells, as shown in Figure a. Also, the typical devices were surrounded by tungsten (W) top‐electrode contact (TEC) and titanium nitride (TiN) bottom‐electrode contact (BEC).…”

Section: Methodsmentioning

confidence: 99%

Investigation on the Scaling Performances of Carbon‐Doped Ge₂Sb₂Te₅ Thin Films for Phase Change Random Access Memory in a 40 nm Process

Yan

Cai

Xue

et al. 2019

Physica Status Solidi (a)

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Herein, the amorphous and crystalline characteristics at different thicknesses for carbon-doped Ge 2 Sb 2 Te 5 (CGST) thin films are systematically investigated. Switching current and grain size of the cubic (face-centered cubic [FCC]) phase both reduce in thinner films, and the 35 nm-thick CGST-based chips can even switch in just 30 ns. Interestingly, high data retention (118 C) is also maintained in 35 nm-thick CGST-based chips, better than the case in Ge 2 Sb 2 Te 5 -based chips (85 C). The endurance ability of more than 10 7 cycles with a resistance ratio of one order of magnitude demonstrates that the 35 nm-thick CGST-based chip is a potential candidate for the application of phase change random access memory.

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Section: Methodsmentioning

confidence: 99%

Investigation on the Scaling Performances of Carbon‐Doped Ge₂Sb₂Te₅ Thin Films for Phase Change Random Access Memory in a 40 nm Process

Yan

Cai

Xue

et al. 2019

Physica Status Solidi (a)

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“…Since these cells are being programmed at the same time, and by using a program-and verify (P&V) scheme with two to three iterations, the effect of thermal crosstalk can be avoided in the BL direction. We remark that a 3-step P&V scheme [8] is widely used in the current PCM, as a single write pulse is typically not enough to take into account the variability of the memory cells within a large array. Therefore, the memory array architecture can be designed to have 256 BLs (or more depending on the parallel programming ability of the circuit) within each tile, the basic architecture of the PCM array, so that the thermal crosstalk can be avoided in the BL direction.…”

Section: Vert Ical Cons Trained Coding In Conjunction With Parallmentioning

confidence: 99%

Vertical constrained coding for phase-change memory with thermal crosstalk

Cai

2014

2014 International Conference on Computing, Networking and Communications (ICNC)

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Phase-change memory (PCM) has been widely con sidered as one of the most promising non-volatile memory (NVM) technologies due to its high scalability and cost effectiveness. A critical reliability issue caused by PCM cell down scaling is the thermal crosstalk, which leads to the change of a cell's state while its adjacent cells are being programmed by a high-current reset pulse. In this paper, we propose novel vertical constrained coding scheme in conjunction with parallel programming to mitigate the thermal crosstalk for PCM in both the bit-line (BL) and word-line (WL) directions. We further propose efficient finite-state encoding methods to design capacity-approaching constrained codes which serve as base codes of the vertical constrained coding scheme.Simulation results show that the proposed schemes can effectively reduce the probability of disturbed bits due to thermal crosstalk, and hence help to push the scaling limitation of PCM. It has also been found that the proposed constrained coding scheme can reduce the probability of the reset state, and thereby improve the endurance of PCM.

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“…RVM [37] is similar in spirit to failure-atomic msync(), though utilizing a different interface and focusing on virtual memory support rather than mapped files. With continuing advances in non-volatile memory (NVRAM) hardware technologies [8,11], recent studies have proposed a new NVRAM-based file system design [10], new data access primitives (including Mnemosyne [44], NV-heaps [9], and CDDS [43]), as well as fast failure recovery [30]. Unfortunately, today's NVRAM manufacturing technologies still suffer from low space density (or high $/GB) and stability/durability problems.…”

Section: Related Workmentioning

confidence: 99%

Failure-atomic msync()

Park

Kelly

Shen

2013

Proceedings of the 8th ACM European Conference on Computer Systems

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Preserving the integrity of application data across updates is difficult if power outages and system crashes may occur during updates. Existing approaches such as relational databases and transactional key-value stores restrict programming flexibility by mandating narrow data access interfaces. We have designed, implemented, and evaluated an approach that strengthens the semantics of a standard operating system primitive while maintaining conceptual simplicity and supporting highly flexible programming: Failureatomic msync() commits changes to a memory-mapped file atomically, even in the presence of failures. Our Linux implementation of failure-atomic msync() has preserved application data integrity across hundreds of whole-machine power interruptions and exhibits good microbenchmark performance on both spinning disks and solid-state storage. Failure-atomic msync() supports higher layers of fully general programming abstraction, e.g., a persistent heap that easily slips beneath the C++ Standard Template Library. An STL built atop failure-atomic msync() outperforms several local key-value stores that support transactional updates. We integrated failure-atomic msync() into the Kyoto Tycoon key-value server by modifying exactly one line of code; our modified server reduces response times by 26-43% compared to Tycoon's existing transaction support while providing the same data integrity guarantees. Compared to a Tycoon server setup that makes almost no I/O (and therefore provides no support for data durability and integrity over failures), failure-atomic msync() incurs a three-fold response time increase on a fast Flash-based SSD-an acceptable cost of data reliability for many.

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A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology

Cited by 26 publications

References 15 publications

Investigation on the Scaling Performances of Carbon‐Doped Ge₂Sb₂Te₅ Thin Films for Phase Change Random Access Memory in a 40 nm Process

Investigation on the Scaling Performances of Carbon‐Doped Ge₂Sb₂Te₅ Thin Films for Phase Change Random Access Memory in a 40 nm Process

Vertical constrained coding for phase-change memory with thermal crosstalk

Failure-atomic msync()

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A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology

Cited by 26 publications

References 15 publications

Investigation on the Scaling Performances of Carbon‐Doped Ge2Sb2Te5 Thin Films for Phase Change Random Access Memory in a 40 nm Process

Investigation on the Scaling Performances of Carbon‐Doped Ge2Sb2Te5 Thin Films for Phase Change Random Access Memory in a 40 nm Process

Vertical constrained coding for phase-change memory with thermal crosstalk

Failure-atomic msync()

Contact Info

Product

Resources

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Investigation on the Scaling Performances of Carbon‐Doped Ge₂Sb₂Te₅ Thin Films for Phase Change Random Access Memory in a 40 nm Process

Investigation on the Scaling Performances of Carbon‐Doped Ge₂Sb₂Te₅ Thin Films for Phase Change Random Access Memory in a 40 nm Process