A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET

Wang, Luke; LaCroix, Marc-Andre; Carusone, Anthony Chan

doi:10.1109/tcsii.2017.2726063

Cited by 18 publications

(5 citation statements)

References 11 publications

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“…To address this issue, the research [3] advises employing a switching capacitor as a level converter to maintain constant V ds . Additionally, to enhance the stability of Equation (1), it is also required to impose a limit on I while maintaining V ds at a constant value. C4 and C5 are also added to reduce current variation, creating a negative feedback loop through the capacitor connected to M4, which can partially suppress the current variation.…”

Section: Amplifiermentioning

confidence: 99%

“…The demand for systems with faster transmission rates and higher signal quality has experienced significant growth as millimeter-wave wireless, radio, and cellular communications continue to expand. This expansion has necessitated the development of broadband ADCs with bandwidths beyond GHz and high accuracy for digitizing Intermediate Frequency (IF) signals or sampling directly at Radio Frequency (RF) [ 1 , 2 , 3 , 4 , 5 ]. In the field of communications protocols, radar scanning, and electronic measurements, the detection and decoding of weak signals play a central role in differentiating system performance.…”

Section: Introductionmentioning

confidence: 99%

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A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS

Guo

Jia

et al. 2023

Micromachines

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This paper presents a single-channel 12-bit, 2 GS/s pipelined analog-to-digital converter (ADC) for wideband sampling receivers. The design adopts a novel source follower input buffer with multiple feedback loops to improve sample linearity and extend bandwidth. Additionally, an improved two stages charge pump amplifier topology is introduced, which doubles the Gain Bandwidth Product (GBW) without consuming additional power. To address the back-end ADC and background calibration, a multi-level dither strategy is employed, utilizing a new high-speed and low-cost uniform distribution pseudorandom code generator. The prototype ADC fabricated in 40 nm CMOS process achieves 68.24 dB SFDR up to Nyquist frequency with a sampling rate of 2 GS/s. Measurement results demonstrate a bandwidth exceeding 5 GHz, resulting in a Schreier FOMs of 152.4 dB.

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Section: Amplifiermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS

Guo

Jia

et al. 2023

Micromachines

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“…Its broad applicability lies in the fact of its architectural simplicity and mid resolution range with moderate power utilization. However, ADC (SAR) is slightly unfit for the applications which require very high speed with high resolution [12], [13]. The count of significant components like comparators, encoders/decoders, pre-amplifiers, registers increases exponentially as the designers go for higher resolution and fast speed [14], [15].…”

Section: Introductionmentioning

confidence: 99%

International Journal of Electronics and Telecommunications

Khatak

Kumar

Dhull

2020

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The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a comparator which is equipped with common mode current feedback and gain boosting technique (CMFD-GB) and a residue amplifier. The proposed 8 bits ADC structure can achieve the speed of 140 megasamples per second. The proposed ADC architecture is designed at a resolution of 8 bits at 10 MHz sampling frequency. DNL and INL values of the proposed design are -0.94/1.22 and -1.19/1.19 respectively. The ADC design dissipates a power of 1.24 mW with the conversion speed of 0.98 ns. The magnitude of SFDR and SNR from the simulations at Nyquist input is 39.77 and 35.62 decibel respectively. Simulations are performed on a SPICE based tool in 90 nm CMOS technology. The comparison shows better performance for this proposed ADC design in comparison to other ADC architectures regarding speed, resolution and power consumption.

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“…Flash analog to digital converters (ADC) are often considered in systems on chip (SoC) applied to high-speed communication interfaces, front-end readout circuits, and data acquisition systems [1], [2]. Due to the highly parallel architecture of a Flash ADC, the analogue input signal is instantaneously compared against all the quantization levels, thus the conversion speed is limited only by the slowest comparator in the array.…”

Section: Introductionmentioning

confidence: 99%

“…Another approach to mitigate parameter variability is based on digitally controlled trimming. In this approach, a set of additional devices (transistors or capacitors) is collectively connected to the critical nodes of a comparator through digitally controlled switches [1], [8]. Alternatively, a digitally controlled bias can be used to achieve similar effect without using redundant devices employing circuit degeneration [9], [10] or body biasing [11].…”

Section: Introductionmentioning

confidence: 99%

Energy Efficient Flash ADC With PVT Variability Compensation Through Advanced Body Biasing

Mroszczyk

Goodacre

Pavlidis

2019

IEEE Trans. Circuits Syst. II

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This paper presents the design of an energy efficient Flash analogue-to-digital converter (ADC) with Threshold Inverter Quantiser (TIQ) comparator employing advanced body biasing to compensate for the effects of parameter variability. The proposed calibration scheme is verified against process, voltage, and temperature (PVT) corners as well as random parameter variability (mismatch). Two proof-of-concept ADCs of 4-and 6bit precision are designed and verified in simulations in 28 nm Fully Depleted Silicon on Insulator (FDSOI) technology. The 6-bit converter achieves sampling rate of 3 GS/s, energy efficiency per conversion step below 20 fJ, and precision of 5.2 effective number of bits (ENOB). The proposed ADC architecture is dedicated to high-speed and low-precision applications, such as communication transceivers and data acquisition systems where area and energy efficiency are paramount. Index Terms-Flash analog-to-digital converter (ADC), offset calibration, threshold inverter quantiser (TIQ), body biasing. This paragraph of the first footnote will contain the date on which you submitted your brief for review. This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 671578.

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A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET

Cited by 18 publications

References 11 publications

A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS

A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS

International Journal of Electronics and Telecommunications

Energy Efficient Flash ADC With PVT Variability Compensation Through Advanced Body Biasing

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