2019 31st International Conference on Microelectronics (ICM) 2019
DOI: 10.1109/icm48031.2019.9021937
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A 4-bit 2ps Resolution Time-to-Digital Converter Utilizing Multi-Path Delay Line for ADPLL

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Cited by 2 publications
(4 citation statements)
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“…Similar to the STDP learning rule, the conductance of the memristor is programmed using temporal ToF information. This method facilitates the storage of the detected ToF information in a physical medium as conductance without requiring complex digital ToF architectures with numerous transistors and capacitors, resulting in a miniaturized system footprint. The neuromorphic 3D sensing also allows for a low power consumption of 0.171 mW for single depth acquisition, which is below the average power consumption of other conventional ToF architectures (0.1–0.65 mW) such as a vernier delay line, multiphase delay line, ring oscillator, and vernier ring oscillator …”
Section: Introductionmentioning
confidence: 96%
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“…Similar to the STDP learning rule, the conductance of the memristor is programmed using temporal ToF information. This method facilitates the storage of the detected ToF information in a physical medium as conductance without requiring complex digital ToF architectures with numerous transistors and capacitors, resulting in a miniaturized system footprint. The neuromorphic 3D sensing also allows for a low power consumption of 0.171 mW for single depth acquisition, which is below the average power consumption of other conventional ToF architectures (0.1–0.65 mW) such as a vernier delay line, multiphase delay line, ring oscillator, and vernier ring oscillator …”
Section: Introductionmentioning
confidence: 96%
“…10−12 This method facilitates the storage of the detected ToF information in a physical medium as conductance without requiring complex digital ToF architectures with numerous transistors and capacitors, resulting in a miniaturized system footprint. The neuromorphic 3D sensing also allows for a low power consumption of 0.171 mW for single depth acquisition, 10 which is below the average power consumption of other conventional ToF architectures (0.1−0.65 mW) such as a vernier delay line, 13 multiphase delay line, 14 ring oscillator, 15 and vernier ring oscillator. 16 NLOS ranging is a promising 3D imaging application based on the ToF principle, which detects indirect optical signals for visualizing hidden objects.…”
Section: ■ Introductionmentioning
confidence: 98%
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“…Basically, the delay line in the Vernier TDC can be roughly divided into three categories. The first kind of delay line is composed of typical inverters without feedback adjustment circuits [ 4 , 5 , 6 , 7 , 8 ]. This kind of delay line has a simple structure, but cannot deal with PVT variations, so its robustness needs to be improved.…”
Section: Introductionmentioning
confidence: 99%