2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) 2013
DOI: 10.1109/bctm.2013.6798172
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A 4.8–6.8GHz phase-locked loop with power optimized design methodology for dividers

Feng Zhao
1
,
Jianjun Yu
2
,
Joseph Cali
3
et al.
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