A 4.5 mW CT Self-Coupled <formula formulatype="inline"><tex Notation="TeX">$\Delta\Sigma$</tex></formula> Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation

Abstract

This paper presents a power-efficient single-loop continuous-time (CT) modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm .

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“…The comparison with the similar works is presented in chronological order. The topologies in [3], [7], [12] present good FoM numbers at the expense of a third-order topology and more quantization levels. These solutions use a calibration scheme and the enhanced performance is the combination of the special techniques.…”

“…Another aspect to be considered is that leakage integrators not only degrade the Signal to Quantization Noise Ratio (SQNR) because of the magnitude influence on the noise transfer function but also change the integrator's frequency response, giving rise to the Excess Loop Delay (ELD). New topologies have been proposed compensating the ELD and the aforementioned inconveniences with more stages in the OTA [7]. Another recent option is the single-amplifier resonator in CT modulators [8], [9].…”

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