A 4.5 GΩ-Input Impedance Chopper Amplifier With Embedded DC-Servo and Ripple Reduction Loops for Impedance Boosting to Sub-Hz

Pham, Xuan Thanh; Duong, Duc Nha; Nguyen, Ngoc Tan; Trưởng, Nguyễn Văn; Lee, Jong‐Wook

doi:10.1109/tcsii.2020.3007934

Cited by 14 publications

(7 citation statements)

References 6 publications

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“…The mid-band gain is 39.5 dB, affected by the parasitics. The result is similar to the gain realized using the metal-insulator-metal (MIM) capacitor in the 180 nm CMOS process [22], indicating the VNCAP has a relatively good matching in the 28 nm process. Fig.…”

Section: Dslsupporting

confidence: 67%

“…The CM voltage V CM = V DD /2 is used to bias G m1 and G m2 using pseudo resistors R HP1,2 and R b1,2 . The G m1 and G m2 consume 800 nA and 180 nA, respectively, to achieve a low-frequency open-loop gain of A V > 80 dB at V DD = 1 V. Two-stage opamp G m3 is used for the integrator in the DSL [22]. The input V in is up-modulated to chopping frequency f CH = 10 kHz by the input chopper CH in and down modulated to baseband by the output chopper CH out .…”

Section: A Amplifier Designmentioning

confidence: 99%

“…Similar to the input, V EOS is up-modulated to the f CH band, and it is partially suppressed by C fb1,2 at the virtual ground. The residual offset can be expressed as [22]. Then, G m1 converts V EOS,ω into a current.…”

Section: A Amplifier Designmentioning

confidence: 99%

“…The V out,OS is averaged and amplified by the integrator of DSL. The output V O,DSL of the DSL is up-modulated by CH DSL , which is subsequently converted to a current by C hp1,2 , thus, canceling out the upmodulated offset current generated by the V EOS [22]. The V EOS depends on both the material and size of the electrodes, and it can be up to 50 mV [24].…”

Section: A Amplifier Designmentioning

confidence: 99%

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Area and Power-Efficient Capacitively-Coupled Chopper Instrumentation Amplifiers in 28 nm CMOS for Multi-Channel Biosensing Applications

Pham

Nguyen

et al. 2021

IEEE Access

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This paper presents two designs of a capacitively-coupled chopper instrumentation amplifier (CCIA) successfully implemented in 28 nm CMOS for biopotential sensing applications. The first design is a compact CCIA using offset-blocking for chopping ripple reduction, DC servo loop (DSL) for electrode offset (V EOS ) suppression, and a high pass filter (HPF) for handling common-mode (CM) artifacts. An inverter-based self-biased input stage is used for noise and power efficiency. The two gain stages of the CCIA achieve a low-frequency open-loop gain > 80 dB. Realized in an area of 0.05 mm 2 , the CCIA handles V EOS up to 50 mV and tolerates CM artifacts up to 1.5 V pp . The CCIA achieves a mid-band gain of 39.5 dB with a 1 kHz bandwidth by consuming 1 µW. The integrated input-referred noise (IRN) over 200 Hz bandwidth is 2.15 µV rms . The second design presents a dual-channel CCIA (DCCIA) using an orthogonal frequency chopping for multi-sensor array applications. An inverter-based input stage is used for noise efficiency. The measured results show that the DCCIA achieves a low-frequency gain of 39.5 dB with a 3-dB bandwidth up to 1 kHz by consuming 0.71 µW per channel. The measured noise density is 136 nV/√Hz with an integrated noise of 2.67 µV rms over 200 Hz bandwidth. The DCCIA suppresses V EOS up to 50 mV using the DSL. Realized in a compact area of 0.04 mm 2 per channel, an excellent gain matching error of 0.29% is achieved with the crosstalk higher than 58 dB between the channels. This work is a measured report on the instrumentation amplifier using, to the best of the authors' knowledge, one of the smallest CMOS process nodes.INDEX TERMS Chopper instrumentation amplifier, nanometer-scale CMOS, biopotential, multi-channel, electrode offset, DC servo-loop, neural signal recording.

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Section: Dslsupporting

confidence: 67%

Section: A Amplifier Designmentioning

confidence: 99%

Section: A Amplifier Designmentioning

confidence: 99%

Section: A Amplifier Designmentioning

confidence: 99%

See 2 more Smart Citations

Area and Power-Efficient Capacitively-Coupled Chopper Instrumentation Amplifiers in 28 nm CMOS for Multi-Channel Biosensing Applications

Pham

Nguyen

et al. 2021

IEEE Access

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“…Unity-gain buffer and active shielding are also used to nullify the MOSFET parasitic capacitance and reject 50/60Hz power line interference (PLI) [ 56 ]. Moreover, chopper-stabilized amplifiers switch input coupling capacitors and pre-charge them through the auxiliary path before the chopping phase, which makes input capacitance decreasing [ 57 , 58 ]. Impedance monitoring sensors based on artificial current injection are also utilized to check ESI change and compensate it for maximizing input impedance [ 59 , 60 ].…”

Section: Miniaturization Techniques For Eeg Recording Hardwarementioning

confidence: 99%

Miniaturization for wearable EEG systems: recording hardware and data processing

2022

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As more people desire at-home diagnosis and treatment for their health improvement, healthcare devices have become more wearable, comfortable, and easy to use. In that sense, the miniaturization of electroencephalography (EEG) systems is a major challenge for developing daily-life healthcare devices. Recently, because of the intertwined relationship between EEG recording and processing, co-research of EEG recording hardware and data processing has been emphasized for whole-in-one miniaturized EEG systems. This paper introduces miniaturization techniques in analog-front-end hardware and processing algorithms for such EEG systems. To miniaturize EEG recording hardware, various types of compact electrodes and mm-sized integrated circuits (IC) techniques including artifact rejection are studied to record accurate EEG signals in a much smaller manner. Active electrode and in-ear EEG technologies are also researched to make small-form-factor EEG measurement structures. Furthermore, miniaturization techniques for EEG processing are discussed including channel selection techniques that reduce the number of required electrode channel and hardware implementation of processing algorithms that simplify the EEG processing stage.

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A Novel Current Density Based Design Approach of Low-Noise Amplifiers

Tarkhan

2022

IEEE Access

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The input-referred noise (IRN) is one of the most crucial performance indicators for analog front-ends (AFEs) of neural recording devices. We present in this paper, a novel design approach for a low-noise amplifier (LNA) based on the transistor optimization method in CMOS technology. Because flicker noise is predominant in neural recording applications, the AFE has been designed so as to meet input-referred flicker noise specifications, whereas thermal noise contributions are monitored and controlled by flicker noise corner frequencies. Transistor optimization is accomplished by using a lookup table that encapsulates its performance based on its current density. Initially, transistors are optimized based on flicker noise performance; later, they may be further optimized based on their size, power consumption, transconductance, or thermal noise contribution. The proposed approach has been validated by designing a folded-cascode amplifier with an IRN ranging from 2 to 8 µV rms . The results of the simulation show that the errors of our design methodology are less than 10%, which is less than those of gm /I D and the inversion coefficient methods. The proposed LNA achieves 2.1 µV rms while consuming 0.83 µW from 1.2 V supply.

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A 4.5 GΩ-Input Impedance Chopper Amplifier With Embedded DC-Servo and Ripple Reduction Loops for Impedance Boosting to Sub-Hz

Cited by 14 publications

References 6 publications

Area and Power-Efficient Capacitively-Coupled Chopper Instrumentation Amplifiers in 28 nm CMOS for Multi-Channel Biosensing Applications

Area and Power-Efficient Capacitively-Coupled Chopper Instrumentation Amplifiers in 28 nm CMOS for Multi-Channel Biosensing Applications

Miniaturization for wearable EEG systems: recording hardware and data processing

A Novel Current Density Based Design Approach of Low-Noise Amplifiers

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