Area and Power-Efficient Capacitively-Coupled Chopper Instrumentation Amplifiers in 28 nm CMOS for Multi-Channel Biosensing Applications

Abstract

This paper presents two designs of a capacitively-coupled chopper instrumentation amplifier (CCIA) successfully implemented in 28 nm CMOS for biopotential sensing applications. The first design is a compact CCIA using offset-blocking for chopping ripple reduction, DC servo loop (DSL) for electrode offset (V EOS ) suppression, and a high pass filter (HPF) for handling common-mode (CM) artifacts. An inverter-based self-biased input stage is used for noise and power efficiency. The two gain stages of the CCIA achieve a low-frequency open-loop gain > 80 dB. Realized in an area of 0.05 mm 2 , the CCIA handles V EOS up to 50 mV and tolerates CM artifacts up to 1.5 V pp . The CCIA achieves a mid-band gain of 39.5 dB with a 1 kHz bandwidth by consuming 1 µW. The integrated input-referred noise (IRN) over 200 Hz bandwidth is 2.15 µV rms . The second design presents a dual-channel CCIA (DCCIA) using an orthogonal frequency chopping for multi-sensor array applications. An inverter-based input stage is used for noise efficiency. The measured results show that the DCCIA achieves a low-frequency gain of 39.5 dB with a 3-dB bandwidth up to 1 kHz by consuming 0.71 µW per channel. The measured noise density is 136 nV/√Hz with an integrated noise of 2.67 µV rms over 200 Hz bandwidth. The DCCIA suppresses V EOS up to 50 mV using the DSL. Realized in a compact area of 0.04 mm 2 per channel, an excellent gain matching error of 0.29% is achieved with the crosstalk higher than 58 dB between the channels. This work is a measured report on the instrumentation amplifier using, to the best of the authors' knowledge, one of the smallest CMOS process nodes.INDEX TERMS Chopper instrumentation amplifier, nanometer-scale CMOS, biopotential, multi-channel, electrode offset, DC servo-loop, neural signal recording.

Noise Analysis and Design Methodology of Chopper Amplifiers With Analog DC-Servo Loop for Biopotential Acquisition Applications

“…The voltage-mode DSL (VM-DSL) [7], [14], [15] and the current-mode DSL (CM-DSL) [7], [23], [24] are two distinct analog DSL implementations used for EDO cancellation as demonstrated in Fig. 5.…”

“…As a result, Z in is commonly less than 10 M in chopper VM-DSL architecture, which is acceptable for general biosensing applications over the skin where relatively large electrodes are used, but it may not be acceptable in deep brain recording implants [38]. Consequently, additional circuit techniques that boost the input impedance may need to be applied in order to mitigate the loading effect and also achieve the required CMRR performance [3], [4], [5], [6], [13], [14], [15].…”

“…To mitigate the mismatch between the capacitors, a chopper is commonly placed in front of input capacitors and another chopper is placed at the output of the amplifier as depicted in Fig. 2(b) [13], [14], [15]. In this way, the common-mode interference that is converted to differential-mode due to mismatches is upconverted to a higher frequency.…”

Design and Analysis of Wideband PNP Sziklai Common Collector Amplifier with High Current Gain

“…A Sziklai pair, also known as Complementary Darlington pair, comprises two BJTs of opposite polarity and their basic advantage is lower base turn-ON voltage (∼625mV) which is almost half as compared to Darlington pair (∼1.36 Volts) (6) . The current gain factor of Sziklai pair (β sziklai =β Q1 β Q2 +β Q1 ) is slightly less than that of Darlington pair (β darlington =β Q1 β Q2 +β Q1 + β Q2 ) due to small amount of in-built negative feedback but for higher β values, current gain factor of both the devices are treated identical (7) . Sziklai pair is much thermal stable than Darlington pair due to lower quiescent current (10mA-100mA).…”

Design a low power, 100dB operational amplifier using CMOS technology

“…Today's system-on-chip (SOC) applications required the integration of both analog and digital components to address non-functional constraints [1][2][3][4][5][6][7][8]. The best-picked topology can aid with the appropriate design of analog and digital circuits.…”