A 4.4 ns CMOS 54×54-b multiplier using pass-transistor multiplexer

Low latency, glitch-free booth encoder-decoder for high speed multipliers

“…Thus, these factors are generated in the body of booth encoder. In most cases the generation of X factor is simpler than 2X factor according to designated truth table for each work [6,7,8,9,10]. Hence, more hardware is needed to generate 2X and the gate level delay will be higher for this factor.…”

“…By attention in previous works, the gate level delay from inputs to partial products for [6,7] and [9] are 5, 5.5 and 4 XOR logic gates, respectively. The MBE architecture of [10] has lower gate level delay in comparison with 3 mentioned works and the delay from inputs to outputs is at most 4 logic gates.…”

“…Most of the CMOS approaches are in the field of radix-4 modified booth encoding (MBE) architecture [4,5,6,7,8,9,10]. So the emphasis in this paper is on the circuit realization of a high speed, low power and low area radix-4 MBE structure.…”

Redundancy management in arithmetic processing via redundant binary representations

“…In light of the above results, it can be seen that for a multiply operation, using the CS3 representation with the compressor presented in [9] is likely to yield the fastest implementations. Note that converting partial products from two's complement format to CS3 format is trivial; it requires no gates at all.…”

“…(i) SD + SD + SD (The cell in [SI is the most efficient to (ii) SD3(-) + SD3(-) + SD3(-) (Newly designed 171) (iii) CS2 + CS2 + CS2 (Newly designed 171) (iv) CS3 + CS3 -+ CS3 (The extremely efficient 4:2 compressor presented in [9] was used) the best of our knowledge, so we layed out this cell.) It can be shown that when adding two CS2 numbers without format conversion, no look-back (right context) is required and a carry set of C(' ") = ( 0 , l ) is sufficient 171.…”