This paper is about the implementation of a novel booth encoder-decoder in a 0.35 µm CMOS technology. By introducing a new truth table, the gate level delay from inputs to partial products is reduced to two XOR logic gates plus one transistor which is the main advantage of the proposed architecture. Also, the gate count is reduced which reduces the power dissipation. In addition, because of similar paths from inputs to outputs, the latency for all paths becomes equal. Therefore, the output waveforms will be free of glitch. Post layout simulations demonstrate that the delay of the whole system is 350 ps.
In this paper the circuit to produce the current mode membership function including OTA and MIN, MAX circuits has been presented. The ability to produce very linear triangular, trapezoidal, s-shape and z-shape functions for applications of neuron-fuzzy programming with controlling voltages is applied. The circuit is designed with simple structure, high dynamic range, low power consumption and area is the speed and accuracy is high. At the end the simulation results with the software HSPICE (49 levels) of 0.35μm CMOS standard processes is presented. Layout of circuits on the surface is about 5μm×36 μm.
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