A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications

Jung, Hae-Kang; Yang, Jin Kyu; Lee, Jeonghun; Ko, Hyeongjun; Lee, Hyuk; Song, Taeksang; Shim, Jae‐Jin; Lee, Sang-Kwon; Song, Keunsoo; Kim, Dongkyun; Kim, Hyungsoo; Kim, Yunsaing

doi:10.1109/vlsic.2015.7231255

Cited by 17 publications

(5 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The proposed transmitter consists of amplifier (AMP), divider (DIV), phase controller, quadrature clock correctors, serializers, external duty cycle detectors (External DCDs) and output drivers (DRVs). The transmitter of DRAM interface [2], [3] has four channel, which consists of 8 data paths and 1 data strobe path. Each channel is synchronized by same clock signal in the conventional transmitter.…”

Section: Circuit Descriptionmentioning

confidence: 99%

A Low EMI Transmitter for DRAM Interface with Quadrature Clock Corrector

Lee

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

This paper presents a transmitter with quadrature clock corrector (QCC) and phase controller for reducing EMI problem. The phase controller consists of phase interpolator and transmission gate (TG). The transmission gate is added to turn function on and off. The quadrature clock corrector is used for signal integrity. The circuit is designed in 180-nm CMOS process using 1.8-V supply. The operating frequency is 3.2 Gbps. For duty cycle distortion of 30% ~ 70% and phase error of ±30 degrees, the maximum duty cycle error of corrected clock is about 0.4%, and the phase error between the OUT0 and OUT90 signal is up to about 3.9 degrees. The duty correction time is about 5ns and phase correction time is about 36ns. And the maximum current peak of output drivers is 23% less than that of conventional transmitter.

show abstract

Section: Circuit Descriptionmentioning

confidence: 99%

A Low EMI Transmitter for DRAM Interface with Quadrature Clock Corrector

Lee

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…As the memory bandwidth required for mobile devices and computing systems for big data processing such as cloud computing and artificial intelligence (AI) increases, the operating frequency of the memory I/O link is continuously increasing. Recent high-speed DRAMS [1,2,5,6,7,8,9,10] and memory controllers [3,4] operating above multi-Gbps demand very precise 50% on-chip duty-cycle clocks to improve timing margins. However, the clock duty-cycle of a memory system is distorted by impedance mismatches, dispersion and crosstalk noise that occur in memory interface channels operating above multiple GHz.…”

Section: Introductionmentioning

confidence: 99%

“…To eliminate the clock duty-cycle errors in memory interface channels, input clock buffers, and on-chip clock trees, typical high-speed DRAM and memory controllers utilize analog-type, digital-type or hybrid-type duty-cycle corrector (DCC) circuits [1,2,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20]. The DCCs in DDR3, DDR4, LPDDR4, LPDDR5, and GDDR5 SDRAM applications performs duty-cycle error compensation of high-speed signal pins for a differential clock (CK/CKb), data signals (DQs), and a data strobe signal (DQS).…”

Section: Introductionmentioning

confidence: 99%

“…Most DCCs used in DRAM applications utilize a small-swing to full-swing level shifter (= also known as a CML-to-CMOS level converter) [24,25] to amplify the small-swing clock signal to full-swing CMOS level [1,2,6,13,20,24,25]. Generally, the conventional level shifter has a problem that is very vulnerable to process corner variation.…”

Section: Introductionmentioning

confidence: 99%

“…Simulated linear duty cycle correction capability of the proposed PFDE according to the V ctrl voltage at 3.4 GHz Layout of the proposed full-swing DCC core IEICE Electronics Express, Vol 16,. No.19,[1][2][3][4][5] …”

mentioning

confidence: 99%

See 2 more Smart Citations

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

Hwang

Kim

2019

IEICE Electron. Express

View full text Add to dashboard Cite

This Letter presents a 0.8-3.4 GHz process variation insensitive full-swing duty-cycle corrector (DCC) for high-speed memory I/O links. The proposed DCC utilizes a new full-swing duty cycle adjuster (DCA) that can provide a full-swing output clock of 50% duty-cycle without using a small-swing to full-swing level shifter. The proposed full-swing DCA is based on a new pseudo-differential feedback delay element (PFDE) and fundamentally eliminates the problem of increased duty-cycle errors due to the use of a level shifter that is vulnerable to process corner variation. The proposed DCC is implemented in a 40-nm CMOS process and achieves an operating frequency range of 0.8-3.4 GHz. The duty-cycle correction range is ²15% at 3.4 GHz. The DCC dissipates 2.8 mW from a 1.0 V supply at 3.4 GHz and occupies an active area of only 0.0054 mm 2 .

show abstract