A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops

Abstract

Nonvolatile processors offer a number of desirable properties including instant on/off, zero standby power and resilience to power failures. This paper presents a fabricated nonvolatile processor based on ferroelectric flip-flops. These flipflops are used in a distributed fashion and are able to maintain system states without any power supply indefinitely. An efficient controller is employed to achieve parallel reads and writes to the flip-flops. A reconfigurable voltage detection system is designed for automatic system backup during power failures. Measurement results show that this nonvolatile processor can operate continuously even under power failures occurring at 20 KHz. It can backup system states within 7 μs and restore them within 3 μs. Such capabilities will provide a new level of support to chip-level fine-grained power management and energy harvesting applications.

Hibernus++: A Self-Calibrating and Adaptive System for Transiently-Powered Embedded Devices

“…Recently, a number of hardware approaches to transient computing have been proposed, which explore Non-Volatile Processor (NVP) architectures [25] to optimise behaviour. Wang et al [26] proposed a NVP using ferroelectric flipflops that incorporate both volatile and non-volatile elements for checkpointing; Bartling et al [27] presented an ARMbased NVP, exploiting SoC FRAM-based logic arrays for state retention, and Sakimura et al [28] presented a 16-bit RISC CPU based on MeRAM. The major advantage of customized NVPs such as these is the significant reduction in time and energy for data retention.…”

A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-$\mu \hbox{m}$ CMOS for Nonvolatile Processing in Digital Systems

“…Interestingly, slightly more than half the energy is associated with the CMOS circuits, which is largely independent of choosing the ferroelectric capacitor as the nonvolatile memory technology. The measurements of energy, save time, restore time, and on-off cycling rate are summarized in Table VII and compared to related work [7]. The improvements in this work's energy per save/restore operation can come from a difference in fecap size and circuit topology.…”

“…The improvements in this work's energy per save/restore operation can come from a difference in fecap size and circuit topology. Also, the proposed NVDFF has no direct current paths from power supply to ground; whereas, [7] precharges the slave latch into a metastable state that can produce significant short circuit current through the cross-coupled inverter pair.…”

“…The improved save/restore timing is suspected to come from (1) the larger voltage bias applied to the ferroelectric capacitors while sensing in the NVDFF and (2) the larger sensing time constant on the latch nodes in [7] because of loading by the fecaps. written data.…”

“…Compared to other nonvolatile technologies, ferroelectric random access memory (FeRAM) has been shown to consume the least amount of energy per read or write operation compared to other nonvolatile memory technologies; although, it has a larger cell area [4]. Several developments in nonvolatile processing have been introduced [5]- [7], but practical challenges related to system integration prevent their widespread use while further improvement in save/restore energy and time can still expand the scope of this technology.…”