A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-V<sub>MIN</sub> Applications

Chang, Jonathan; Chen, Yen-Huei; Chan, Gary; Lin, Kuo-Ping; Wang, Po-Sheng; Lin, Y. C.; Chen, S. C.; Lin, Po-Yao; Wu, Cheng‐Yu; Lin, C.K.; Nien, Yi-Hsin; Fujiwara, Haruhiko; Katoch, A.; Lee, Robin; Liao, Haijun; Liaw, J.J.; Wu, Shien‐Yang; Li, Quincy

doi:10.23919/vlsitechnologyandcir57934.2023.10185287

Cited by 5 publications

(3 citation statements)

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“…At the top level of the hierarchy, there is a global buffer that has a capacity in the range of 1-100 MB, which is implemented by static random-access memory (SRAM) cache in conventional designs (Supplementary Information section 1). It is known that SRAM is widely used as the mainstream onchip buffer memory for CPU or GPU thanks to its fast access (less than a few nanoseconds), unlimited endurance (>10 16 cycles) and superior scalability with the leading edge node logic process (to today's 3 nm node and beyond) 7,8 . However, SRAM is an expensive technology (in terms of the silicon footprint with a relatively low integration density of dozens of megabits per millimetre squared), and also suffers from high stand-by leakage power (tens to hundreds of picowatts per bit) 7,8 .…”

Section: Review Articlementioning

confidence: 99%

“…It is known that SRAM is widely used as the mainstream onchip buffer memory for CPU or GPU thanks to its fast access (less than a few nanoseconds), unlimited endurance (>10 16 cycles) and superior scalability with the leading edge node logic process (to today's 3 nm node and beyond) 7,8 . However, SRAM is an expensive technology (in terms of the silicon footprint with a relatively low integration density of dozens of megabits per millimetre squared), and also suffers from high stand-by leakage power (tens to hundreds of picowatts per bit) 7,8 . Hence, it is intriguing to explore alternative high-speed memory candidates for the global buffer.…”

Section: Review Articlementioning

confidence: 99%

“…3a, for the 3 nm high-performance cloud server where the compute activity is high -that is, with 100% of the inference queries constantly fed in -SRAM global buffer is still a competitive candidate for high energy efficiency. Thanks to the continued scaling of the SRAM bit cell area (Supplementary Information section 1) down to 0.021 µm 2 at 3 nm node 8 , a large capacity of SRAM (up to 32 MB 8 ) is an available product from the foundries. The 2T gain cell is also a good candidate with energy efficiency comparable with SRAM.…”

Section: Tpu Buffer Memory Case Study and Neurosim Benchmarkingmentioning

confidence: 99%

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High-speed emerging memories for AI hardware accelerators

Lu,

Lee,

Kim

et al. 2024

Nat Rev Electr Eng

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Applications of artificial intelligence (AI) necessitate AI hardware accelerators able to efficiently process data-intensive and computationintensive AI workloads. AI accelerators require two types of memory: the weight memory that stores the parameters of the AI models and the buffer memory that stores the intermediate input or output data when computing a portion of the AI models. In this Review, we present the recent progress in the emerging high-speed memory for AI hardware accelerators and survey the technologies enabling the global buffer memory in digital systolic-array architectures. Beyond conventional static random-access memory (SRAM), we highlight the following device candidates: capacitorless gain cell-based embedded dynamic random-access memories (eDRAMs), ferroelectric memories, spin-transfer torque magnetic random-access memory (STT-MRAM) and spin-orbit torque magnetic random-access memory (SOT-MRAM). We then summarize the research advances in the industrial development and the technological challenges in buffer memory applications. Finally, we present a systematic benchmarking analysis on a tensor processing unit (TPU)-like AI accelerator in the edge and in the cloud and evaluate the use of these emerging memories. Sections• Leading edge node SRAM is still a competitive high-performance technology for AI hardware in the cloud, whereas emerging memories exhibit more advantages in AI hardware at the edge where minimizing the stand-by leakage power is critical.Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

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Section: Review Articlementioning

confidence: 99%