A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing

Abstract

Abstract-This paper introduces a 3D-stacked logic-in-memory (LiM) system that integrates the 3D die-stacked DRAM architecture with the application-specific LiM IC to accelerate important data-intensive computing. The proposed system comprises a fine-grained rank-level 3D die-stacked DRAM device and extra LiM layers implementing logic-enhanced SRAM blocks that are dedicated to a particular application. Through silicon vias (TSVs) are used for vertical interconnections providing the required bandwidth to support the high performance LiM computing. We performed a comprehensive 3D DRAM design space exploration and exploit the efficient architectures to accelerate the computing that can balance the performance and power. Our experiments demonstrate orders of magnitude of performance and power efficiency improvements compared with the traditional multithreaded software implementation on modern CPU.

Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory

“…The re-gridding and FFT units are implemented in the logic layer of a 3D-stacked DRAM similar to [15], [16]. The 2D-FFT requires double-buffered local memory that performs data permutations and a local FFT core that executes the FFT kernel [13], [16].…”

Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware

“…And we used CACTI-3DD, a 3D die-stacked DRAM modeling tool to explore 3D DRAM design space in terms of area, power and bandwidth [9]. The design details can be found in another accompanying work [27]. Here we exploit one of the optimal 3D-DRAM design points, that is, a 8 Gb 3D-stacked DRAM system composed of four stacked DRAM dies [2], [13].…”

FFTS with near-optimal memory access through block data layouts

“…There have been many implementations of single and multidimensional FFTs on various platforms. These include software implementations on CPUs [3,4], GPUs [5], supercomputers [6,7], and hardware implementations [8,9,10]. These implementations either do not address the memory access pattern issue or provide a solution for a specific target platform and problem.…”