A 3D stacked CMOS image sensor with 16Mpixel global-shutter mode and 2Mpixel 10000fps mode using 4 million interconnections

Kondô, Torû; Takemoto, Y.; Kono, Kenji; Tsukimura, Mitsuhiro; Takazawa, Naohiro; Kato, Hideki; Suzuki, Satoshi; Aoki, Jun; Saito, Haruhisa; Gomi, Yuichi; Matsuda, Shôichi; Tadaki, Yoshitaka

doi:10.1109/vlsic.2015.7231335

Cited by 31 publications

(8 citation statements)

References 3 publications

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“…Finally, in the near future SPAD-based imagers could definetely take advantage of the advent of 3D-stacked fabrication technologies exploiting the co-integration of specialized CIS back-side illuminated sensing layer with deep-submicron digital CMOS. BSI-compatible SPADs offer higher sensitivity in the NIR region that combined with the stacking on advanced digital CMOS technologies will enable the realisation of pixel pitches in the order of a few micrometers and high fill factor [ 40 , 41 ]. At the same time efficient processing of the generated data flow will still be possible.…”

Section: Discussionmentioning

confidence: 99%

Compact SPAD-Based Pixel Architectures for Time-Resolved Image Sensors

Perenzoni

Pancheri

Stoppa

2016

Sensors

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This paper reviews the state of the art of single-photon avalanche diode (SPAD) image sensors for time-resolved imaging. The focus of the paper is on pixel architectures featuring small pixel size (<25 μm) and high fill factor (>20%) as a key enabling technology for the successful implementation of high spatial resolution SPAD-based image sensors. A summary of the main CMOS SPAD implementations, their characteristics and integration challenges, is provided from the perspective of targeting large pixel arrays, where one of the key drivers is the spatial uniformity. The main analog techniques aimed at time-gated photon counting and photon timestamping suitable for compact and low-power pixels are critically discussed. The main features of these solutions are the adoption of analog counting techniques and time-to-analog conversion, in NMOS-only pixels. Reliable quantum-limited single-photon counting, self-referenced analog-to-digital conversion, time gating down to 0.75 ns and timestamping with 368 ps jitter are achieved.

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Section: Discussionmentioning

confidence: 99%

Compact SPAD-Based Pixel Architectures for Time-Resolved Image Sensors

Perenzoni

Pancheri

Stoppa

2016

Sensors

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“…This model of the system provides an enhanced level of accuracy at the output with less amount of unwanted noise signal. The most effected parameter of this system is the channel resistance which in turn detoriates the overall performance of the system [35][36][37][38][39][40][41][42][43][44][45][46].…”

Section: Design and Implementation Of The Soc Based Smart Cmos Pixmentioning

confidence: 99%

An Innovative Design Approach of SoC Based Smart CMOS Sensor for Mixed Signal Processing based Applications

Tiwari¹

2017

IJET

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Abstract-The CMOS based sensor design technology has evolved with tremendous applications in MSP domain with enhanced characteristic of maximized S/N ratio. This feature has been obtained with the utilization of pixel-based amplification in addition to minimizing the presence of the noise at the output of the device. It means that the noise present in the various active device of the system has been suppressed with the help of SoC based design technique i.e. three level pixel implementation. This system basically supports all the SoC components such as feedback amplifier, buffers, tapered reset device, etc. The CMOS based smart system has both software as well as hardware modules which in turn behave as a complete system on chip (SoC) and has got tremendous use in mixed signal based applications. The main application fo this system is in the computational analysis of the various images captured from the real world. The author present a novel approach of implementing a smart system based on SoC design approach with required performance in the domain of mixed signal processing. The simulation of the system has been carried out on LabVIEW with optimum results desired. Some the result has been carried with mathematical modeling based approach using MatLAB software. The minimum S/N ratio of the system is 55 dB with 1920 X 1080 frame readout at 550 Hz. Keywords: CMOS sensor, HDTV, FPA, CCD, APS, SoC, LabVIEW, MatLAB, PID algorithm, MSP, CCD.I. INTRODUCTION The advent of the sensor dependent image processing technology has come into existence late back to 1970's with the use of MOS devices. The functioning of this system primarily depends on the utilization of array of image sensors which in turns rely on the proper functioning of the array of CCD technology so as to provide better and enhanced quality imaging arrays. With further advancement in this technology i.e. with the availability of CMOS based smart sensors, the analysis of the image becomes quite simple, cost effective, enhanced accuracy of the results. In this system, CMOS readouts with millions pixel capacity are used in addition to the detector arrays with the help of flip chip fabrication technology i.e. the most important feature of a SoC design based system. The above fig 1 shows the schematic arrangement i.e. crossectional view of the CMOS sensing system.The system on chip design based systems are normally follows the Moore's Law which utilized CMOS technology so as to produce higher performance sensors in various range of visibility. Due to this reason, CMOS technology without any doubt has now emerged the most common approach for the design of both infrared and visible range sensors that in turn finds enormous applications in the domain of MSP. Based on this features, it has been found that most of the mixed signal processing based industrial applications are still dependent on CMOS Image Sensors (CIS) technology as compared to CCD approach [2][3][4][5][6][7][8].

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“…Advancement of CMOS image sensor (CIS) technology and device integration, particularly backside illumination (BSI) technology and high-density wafer-to-wafer connection technology [4]- [6], allows implementation of a variety of HDR schemes within a practical pixel size. In this article, basic performance requirements to the automotive application are discussed in Section II, and the introduction of HDR technologies of CMOS image sensors and discussions for the automotive application will be given in Sections III and IV, respectively, and the conclusion will be given in Section V.…”

Section: Introductionmentioning

confidence: 99%

HDR CMOS Image Sensors for Automotive Applications

Takayanagi¹,

Kuroda

2022

IEEE Trans. Electron Devices

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Because of various purposes and high dynamic range (HDR) of brightness of objects in automotive applications, HDR image capture is a primary requirement. In this article, HDR CMOS image sensor (CIS) technology and its automotive applications are discussed including application requirements, basic HDR approaches and trends of HDR CMOS image sensor technologies, advantages and disadvantages for automotive application, and future prospect of the HDR technology. LED flicker caused by time aliasing effect and motion artifacts are two major issues in conventional multiple exposure HDR (MEHDR) approach, and several HDR technologies have been introduced for automotive applications. The advancements of image sensor fabrication technology, for instance, backside illumination (BSI) process and pixel level hybrid wafer bonding, have created new trends in the HDR technology.

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A 3D stacked CMOS image sensor with 16Mpixel global-shutter mode and 2Mpixel 10000fps mode using 4 million interconnections

Cited by 31 publications

References 3 publications

Compact SPAD-Based Pixel Architectures for Time-Resolved Image Sensors

Compact SPAD-Based Pixel Architectures for Time-Resolved Image Sensors

An Innovative Design Approach of SoC Based Smart CMOS Sensor for Mixed Signal Processing based Applications

HDR CMOS Image Sensors for Automotive Applications

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