A 3D SoC design for H.264 application with on-chip DRAM stacking

Zhang, Tao; Wang, Kui; Yao, Feng; Chen, Yan; Li, Qun; Lei, Lei; Xie, Jing; Song, Xi; Duan, Lian; Xie, Yuan; Xu, Cheng; Lin, Youn-Long

doi:10.1109/3dic.2010.5751446

Cited by 19 publications

(17 citation statements)

References 13 publications

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“…Zhang et al [2010] proposed a parallel-access mechanism in which two separate DDR Finite State Machines (FSMs) are used to control eight memory channels of a 3D-DRAM. The proposed architecture by Loi and Benini [2010] has every processing element allocated to its own local DRAM channel with a memory controller, and a custom crossbar is used to route incoming traffic from other processing elements.…”

Section: Related Workmentioning

confidence: 99%

A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels

Gomony

Åkesson

Goossens

2015

ACM Trans. Embed. Comput. Syst.

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Ever-increasing demands for main memory bandwidth and memory speed/power tradeoff led to the introduction of memories with multiple memory channels, such as Wide IO DRAM. Efficient utilization of a multichannel memory as a shared resource in multiprocessor real-time systems depends on mapping of the memory clients to the memory channels according to their requirements on latency, bandwidth, communication, and memory capacity. However, there is currently no real-time memory controller for multichannel memories, and there is no methodology to optimally configure multichannel memories in real-time systems. As a first work toward this direction, we present two main contributions in this article: (1) a configurable real-time multichannel memory controller architecture with a novel method for logical-to-physical address translation and (2) two design-time methods to map memory clients to the memory channels, one an optimal algorithm based on an integer programming formulation of the mapping problem, and the other a fast heuristic algorithm. We demonstrate the real-time guarantees on bandwidth and latency provided by our multichannel memory controller architecture by experimental evaluation. Furthermore, we compare the performance of the mapping problem formulation in a solver and the heuristic algorithm against two existing mapping algorithms in terms of computation time and mapping success ratio. We show that an optimal solution can be found in 2 hours using the solver and in less than 1 second with less than 7% mapping failure using the heuristic for realistically sized problems. Finally, we demonstrate configuring a Wide IO DRAM in a high-definition (HD) video and graphics processing system to emphasize the practical applicability and effectiveness of this work. ACM Reference Format:Manil Dev Gomony, Benny Akesson, and Kees Goossens. 2015. A real-time multichannel memory controller and optimal mapping of memory clients to memory channels.

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Section: Related Workmentioning

confidence: 99%

A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels

Gomony

Åkesson

Goossens

2015

ACM Trans. Embed. Comput. Syst.

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“…The use of through silicon vias (TSVs) or monolithic interdie vias enables heterogeneous stacking of multiple dice with very large bandwidth and low energy communication, which improves system performance [2], [3]. However, there are thermal challenges and potential show stoppers due to higher total power density and larger thermal resistance for the dice within the stack [4], [5].…”

Section: -D Integration Is An Emerging Technology To Addressmentioning

confidence: 99%

Thermal Design and Constraints for Heterogeneous Integrated Chip Stacks and Isolation Technology Using Air Gap and Thermal Bridge

Zhang

Bakir

2014

IEEE Trans. Compon., Packag. Manufact. Technol.

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This paper summarizes the thermal challenges in conventional 3-D stacks and proposes a novel stacking structure that eases the thermal problem. The objective of this paper is first to define limits and opportunities for developing different 3-D chip stacks from a thermal perspective, and second to explore our proposed system as a function of microbumps, through silicon vias, die thickness, and other design parameters. In our proposed 3-D stack, the interposer integrated microfluidic heat sink serves as the main heat sink. To thermally decouple stacked dice, we propose air gap isolation between them and a thermal bridge on top of the stack to cool down the isolated die. To evaluate the thermal benefits of the stack, a thermal model is developed based on the finite difference method. Several chip stack scenarios are studied and the simulations are conducted with a processor power of 74.63 W/cm 2 and memory power of 2.82 W/cm 2 . The proposed architecture yielded processor and memory temperatures of 64°C and 40°C, respectively, compared with 76°C and 75°C for the air cooled stack. Index Terms-3-D integrated circuit (3-D IC), dynamic random-access memory (DRAM), microbumps, microfluidic heat sink (MFHS), multicore processor, through silicon vias (TSVs).

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“…A 64-core processor [11] with stacked memory was designed; its maximum throughput is 63.8 GB/s. Zhao et al [12] introduced a five-tier stacked H.264 application using on-chip DRAM stacking. Although memory power is not given in [12], we can figure it out by [13] using the characteristics given in [12].…”

Section: Introductionmentioning

confidence: 99%

“…Zhao et al [12] introduced a five-tier stacked H.264 application using on-chip DRAM stacking. Although memory power is not given in [12], we can figure it out by [13] using the characteristics given in [12]. Thus, the memory power is 492.5 mW, which is still considerably high.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Motion Estimation Processor with 3D Stacked Memory

Zhang

Zhou

Goto

2015

IEICE Trans. Fundamentals

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Motion estimation (ME) is a key encoding component of almost all modern video coding standards. ME contributes significantly to video coding efficiency, but, it also consumes the most power of any component in a video encoder. In this paper, an ME processor with 3D stacked memory architecture is proposed to reduce memory and core power consumption. First, a memory die is designed and stacked with ME die. By adding face-to-face (F2F) pads and through-silicon-via (TSV) definitions, 2D electronic design automation (EDA) tools can be extended to support the proposed 3D stacking architecture. Moreover, a special memory controller is applied to control data transmission and timing between the memory die and the ME processor die. Finally, a 3D physical design is completed for the entire system. This design includes TSV/F2F placement, floor plan optimization, and power network generation. Compared to 2D technology, the number of input/output (IO) pins is reduced by 77%. After optimizing the floor plan of the processor die and memory die, the routing wire lengths are reduced by 13.4% and 50%, respectively. The stacking static random access memory contributes the most power reduction in this work. The simulation results show that the design can support real-time 720p @ 60 fps encoding at 8 MHz using less than 65 mW in power, which is much better compared to the state-of-the-art ME processor. key words: 3DIC design, motion estimation processor, low power design, memory stacking

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A 3D SoC design for H.264 application with on-chip DRAM stacking

Cited by 19 publications

References 13 publications

A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels

A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels

Thermal Design and Constraints for Heterogeneous Integrated Chip Stacks and Isolation Technology Using Air Gap and Thermal Bridge

Low-Power Motion Estimation Processor with 3D Stacked Memory

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