A 3bit/cell nonvolatile memory with crystalline In-Ga-Zn-O TFT

Nagatsuka, Shuhei; Matsuzaki, Takashi; Inoue, Hiroyuki; Ishizu, Tomoko; Onuki, Tatsuya; Ando, Yasuhisa; Nei, Kosei; Miyairi, Hiroo; Atsumi, Tomoaki; Shionoiri, Yutaka; Kimura, Kiyoshi; Okuda, Takashi; Koyama, Jun; Yamazaki, Shunpei

doi:10.1109/imw.2013.6582131

Cited by 22 publications

(20 citation statements)

References 4 publications

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“…In 2010, we developed a nonvolatile memory circuit utilizing the extremely low off-state current, and after that, we fabricated a normally off CPU, a nonvolatile memory, and the like as application examples. [18][19][20][21][22][23][24][25] In the field of LSIs, ULSI formed by microfabrication technologies at several tens of nm level is mainly used. The CAAC-IGZO transistors we have reported so far are at higher than or equal to 0.45 µm level.…”

Section: Introductionmentioning

confidence: 99%

Electrical characteristics and short-channel effect of c-axis aligned crystal indium gallium zinc oxide transistor with short channel length

Kobayashi

Matsuda

Matsubayashi

et al. 2014

Jpn. J. Appl. Phys.

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A channel length of a c-axis aligned crystal indium gallium zinc oxide (CAAC-IGZO) transistor having low off-state current at a yA/µm level was decreased to 100 nm, and the electrical characteristics and short-channel effect of the CAAC-IGZO transistor were researched. As a result, we found that, in the CAAC-IGZO transistor with L = 100 nm, even with a gate insulator film having an equivalent oxide thickness (EOT) = 11 nm, an extremely small off-state current of 380 yA/µm at 85 °C is maintained, in addition channel length dependence of the electrical characteristics is hardly seen. Favorable values of characteristics of the CAAC-IGZO transistor can be obtained, such as subthreshold slope (SS) = 77 mV/dec, drain induced barrier lowering (DIBL) = 73 mV/V, threshold voltage (V th) = 0.65 V, and on-state current (I on) = 65 µA/µm. These results suggest the possibility that the CAAC-IGZO transistor can be applied to an LSI in a deep submicron region.

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Section: Introductionmentioning

confidence: 99%

Electrical characteristics and short-channel effect of c-axis aligned crystal indium gallium zinc oxide transistor with short channel length

Kobayashi

Matsuda

Matsubayashi

et al. 2014

Jpn. J. Appl. Phys.

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“…Further, the proposed memory circuit has a structure similar to that of DRAM; however, it features no refresh; this is achieved by utilizing the extremely low leakage current characteristics of the oxide semiconductor. On a similar note, T. Matsuzaki et al designed a 1 Mb random access memory (RAM) using an oxide semiconductor [1][2][3]. However, these studies showed that a memory cell comprises one single-crystal Si transistor, one oxide thin film transistor (Ox-TFT), and a capacitor.…”

Section: Introductionmentioning

confidence: 99%

P‐50: Development of Multilevel Memory Consisting of Oxide TFTs

Yun

Lee

et al. 2017

Symp Digest of Tech Papers

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This paper proposes a multilevel memory circuit with a simple structure composed of two oxide thin film transistors (Ox-TFTs) and one capacitor. The proposed memory circuit utilizes low leakage current characteristics of the Ox-TFT. Simulation and measurement results confirm that the proposed memory circuit can achieve multilevel memory feature. Author Keywordsmultilevel memory; oxide thin film transistor (Ox-TFT); low leakage current P-50 / S.-H. Yun SID 2017 DIGEST • 1427

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“…Using a hybrid process technology that involves a CAAC-IGZO FET and CMOS FET, applications to large-scale integration (LSI), such as nonvolatile memory (nonvolatile oxide semiconductor RAM, NOSRAM) [19]- [22], CPUs [23]- [28], and an image sensor [29] have also been proposed. In such LSIs, the ultralow off-state current of a CAAC-IGZO FET is utilized effectively for nonvolatile memory cells [19]- [22], nonvolatile registers [23]- [28], and a charge retention node [29] with excellent charge retention characteristics.…”

Section: Introductionmentioning

confidence: 99%

Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register

Aoki

Okamoto

Nakagawa

et al. 2015

IEEE J. Solid-State Circuits

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Normally-off computing (Noff computing) using a multicontext field programmable gate array (MC-FPGA) consisting of crystalline oxide semiconductor FETs has been developed. The Noff computing discussed in this paper is a control architecture for an MC-FPGA capable of performing fine-grained power gating on each programmable logic element (PLE) whose registers include a volatile register and also a nonvolatile shadow register for storing and loading data in the volatile register. The MC-FPGA performs fine-grained control of power supplied only to PLEs contributing to effective calculation, when context switching happens. With an MC-FPGA fabricated with a hybrid process of a 1.0 µm crystalline oxide semiconductor FET on a 0.5 µm CMOS FET, it has been confirmed that the proposed Noff computing can resume the previous task when a context switches back to it, increases PLE use efficiency, and reduces the power consumption by 27.7% at operating frequencies of 20 MHz with a driving voltage of 2.5 V.Index Terms-CAAC-IGZO, crystalline IGZO, crystalline oxide semiconductor, field programmable gate array, multicontext, nonvolatile memory, normally-off computing, oxide semiconductor, power gating, shadow register. 0018-9200

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A 3bit/cell nonvolatile memory with crystalline In-Ga-Zn-O TFT

Cited by 22 publications

References 4 publications

Electrical characteristics and short-channel effect of c-axis aligned crystal indium gallium zinc oxide transistor with short channel length

Electrical characteristics and short-channel effect of c-axis aligned crystal indium gallium zinc oxide transistor with short channel length

P‐50: Development of Multilevel Memory Consisting of Oxide TFTs

Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register

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