42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356)
DOI: 10.1109/mwscas.1999.867285
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A 36-bit balanced moduli MAC architecture

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Cited by 8 publications
(9 citation statements)
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“…Our new MAC architecture, which is described in detail in [2] uses index-transform based approach. The relatively prime moduli in any arbitrary moduli set take any of the three forms p, 2 m , and p m , or a factorable modulus with any of these factors, where p is prime and m is any integer.…”
Section: The Multiply-accumulate Unitmentioning
confidence: 99%
“…Our new MAC architecture, which is described in detail in [2] uses index-transform based approach. The relatively prime moduli in any arbitrary moduli set take any of the three forms p, 2 m , and p m , or a factorable modulus with any of these factors, where p is prime and m is any integer.…”
Section: The Multiply-accumulate Unitmentioning
confidence: 99%
“…That is, we will compute C J (n) wholly within the RNS. n is represented as (5,8,3,4,14,17) by this set of moduli. First, compute C J (n) moduli 7, 17, and 23, and C K (n) moduli 11, 13, and 19 using (15) and (17):…”
Section: Rns Scaling Methodsmentioning
confidence: 99%
“…• They offer high-performance implementations of arithmetic-intensive applications at reduced power supply voltages, important for mobile and wearable computer and communication systems [4] • They avoid lengthy on-chip interconnects, which now represent the major constraint on the realisation of high-performance digital VLSI circuits [5] • They afford hardware-efficient complex multipliers ("QRNS multiplication") comprising two independent multiplications instead of four multiplications and two additions [1] • The component arithmetic operations in an RNS implementation can, without exception, be reduced to short adders and small look-up tables [1] All the items in the above list are applicable to custom VLSI implementations, and the last two also apply advantageously to FPGA implementations [6,7]. Recent industrial interest in RNS confirms the existence and scale of problems faced in implementing DSP algorithms in digital microelectronic fabrics at high clock rates but with low power consumption.…”
Section: Background and Motivationmentioning
confidence: 99%
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