DOI: 10.1109/isscc.1983.1156551
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Abstract: photosite, 3533-element CCD line imager. The chip was designed in 1.2" long silicon, utilizing two-phase two-level polysilicon gate buried channel technology. Quadrilinear shift registers were implemented to achieve the high resolution, while using moderate design rules for better yield. Complete parallel charge transfer was ensured by employing a structure that eliminated the narrow channel effect. Peripheral and video processing circuits were intergrated on the chip.Conventional CCD line imagers use two rea…

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