A 3533 element quadrilinear CCD imager

Abstract

photosite, 3533-element CCD line imager. The chip was designed in 1.2" long silicon, utilizing two-phase two-level polysilicon gate buried channel technology. Quadrilinear shift registers were implemented to achieve the high resolution, while using moderate design rules for better yield. Complete parallel charge transfer was ensured by employing a structure that eliminated the narrow channel effect. Peripheral and video processing circuits were intergrated on the chip.Conventional CCD line imagers use two readout shift registers. The maximum pixel density of this bilinear design is limited by the minimum poly overlap and spacing design rules in the shift registers. The pixel density can be increased by employing a quadrilinear shift register organization' (Figure 1) to relieve these design rule constraints. However, as the imager resolution and the pixel density increase even further, a new limitation arises due to the narrowing of the CCD parallel transfer channels. This is illustrated in Figure 2, curve A, which shows a conventional quadrilinear cell layout. The charge transfer from the inner shift register to the outer shift register is through the field isolated channel A. The inner shift register has essentially no field confinement in the X direction. For an ultra-high resolution imager, the width of channel A, as confined by the field, is very narrow. This causes a reduction of minimum potential due to the narrow channel effect'. A potential barrier that hinders the charge transfer from the inner shift register to channel A is thus created. The measured minimum potential variation versus the channel width for this conventional design is illustrated in Figure 3, curve A. This curve shows that the minimum potential =tarts t o decrease at l o p channel width. At less than 2 p channel vidth the buried channel changes t o the surface channel.A parallel charge transfer technique was devised to eliminate the charge trapping due to the potential barrier; Figure 2, curve B. The design utilizes the barrier gate in the serial transfer direction t o isolate the charge in the parallel transfer direction also. This poly gate isolation is free from bird's beak and field implant encroachment. Therefore, almost no narrow channel effect occurs. The measured minimum potential versus channel width is illustrated in Figure 3, curve B. This curve shows that the minimum potential is constant down to 4 p channel width.Several peripheral and video processing circuits were integrated on chip to achieve lower overall system cost. These include the clock circuits for the charge detection and the sampling, the Function of Quadrilinear CCD Imager", Electronics Letter, 'Herbst. H. and Pfleiderer, H.J., "Modulation Transfer 2Venkateswaran, V., "Effect of Channel Potential Modulation in Narrow Channel CCD Shift Registers", Proc. IEDM,

New technologies in dual channel read-out registers for high-density CCD image sensor

“…Figure 6 shows improved transfer gate pattern. Transfer gate channel width W is defined by the length of storage electrode formed by the 2nd polysilicon layer not by the channel stop separation (6). The polysilicon electrode length is shorter than the channel stop separation, so no potential dip and barrier appears.…”