A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM

Iwata, Y.; Imamiya, K.; Sugiura, Yuki; Nakamura, Hiroshi; Oodaira, H.; Momodomi, M.; Itoh, Y.; Watanabe, T.; Araki, Hirohiko; Narita, Kazuo; Masuda, Keisuke; Miyamoto, Junichi

doi:10.1109/4.475702

Cited by 16 publications

(2 citation statements)

References 3 publications

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“…When there are more than 2 V TH distributions, multiple basic reading operations are performed at different gate voltages. Historically, the first reading technique used the parasitic capacitor of the bitline to integrate cell's current [5][6][7].…”

Section: Readmentioning

confidence: 99%

3D Stacked NAND Flash Memories

Micheloni

Crippa

2016

3D Flash Memories

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In planar Flash memories the most popular memory cell is based on the Floating Gate (FG) technology, whose cross section is shown in Fig. 3.1. Cross section and the associated floating gate model are sketched in Fig. 3.2. Basically, a MOS transistor is built with two overlapping gates: the first one (FG) is completely surrounded by oxide, while the second one forms the Control Gate (CG) terminal. The isolated gate constitutes an excellent "trap" for electrons, enabling long charge retention. The operations used to inject and remove electrons from the isolated gate are called Program and Erase, respectively. These operations modify the threshold voltage V TH of the memory cell, which is, at the end of the day, a MOS transistor. By applying a fixed voltage to the cell's terminals, it is then possible to discriminate two storage levels: when the gate voltage is higher than V TH , the cell is ON ("1"), vice versa it is OFF ("0").To minimize the space on silicon, memory cells are packed together to form a matrix. Depending on how the cells are organized inside the matrix, it is possible to distinguish between NAND and NOR Flash memories. NAND memories are the most widespread in the storage systems; NOR architecture is described in great details in [1].In the NAND string, memory cells are connected in series, in groups of 32, 64, 128, or even 150 [2], as shown in Fig. 3.3. Two select transistors are placed at the edges of the string, to ensure the connection to the source line (through M SL ) and to

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Section: Readmentioning

confidence: 99%

3D Stacked NAND Flash Memories

Micheloni

Crippa

2016

3D Flash Memories

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“…Therefore, the transistor parameters, such as channel length, the oxide thickness, the threshold voltage, and the drain breakdown voltage, have to be tuned to sustain operation and the usual device scaling cannot be adopted for them. In order to solve this problem, a multitransistor process has been introduced for 3.3-V operation Flash memories [1], [2], [4], [5]. While a transistor is optimized with a device scaling for of 3 the program and the erase.…”

Section: Introductionmentioning

confidence: 99%

Circuit techniques for 1.5-V power supply flash memory

Otsuka

Horowitz

1997

IEEE J. Solid-State Circuits

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We describe circuit techniques for a Flash memory which operates with a V DD of 1.5 V. For the interface between the peripheral circuits and the memory core circuits, two types of level shifter circuits are proposed which convert a V DD level signal into the high voltage signals needed for high performance. In order to improve the read performance at a low V DD , a new self-bias bitline voltage sensing scheme is described. This circuit greatly reduces the delay's dependence on bitline capacitance and achieves 19 ns reduction of the sense delay at low voltages. Multilevel storage sensing with this circuit is also discussed.

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Introduction

2015

Nand Flash Memory Technologies

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A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM

Cited by 16 publications

References 3 publications

3D Stacked NAND Flash Memories

3D Stacked NAND Flash Memories

Circuit techniques for 1.5-V power supply flash memory

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