A 35-mW 30-dB Gain Control Range Current Mode Linear-in-Decibel Programmable Gain Amplifier With Bandwidth Enhancement

Kumar, Thangarasu Bharatha; Ma, Kaixue; Yeo, Kiat Seng; Yang, Wanlan

doi:10.1109/tmtt.2014.2364221

Cited by 19 publications

(12 citation statements)

References 25 publications

(35 reference statements)

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“…The key idea of JM is to utilize the useful messages to modulate the energy of the jamming signals. Specifically, a PGA, whose amplification factor can be programmable with digital messages [15]- [17], is adopted at the TN such that it is able to communicate with the RN by modulating its own messages over the jamming signals. The JM method can be briefly described in the following three steps:…”

Section: A Jm Methodsmentioning

confidence: 99%

Jamming Modulation: An Active Anti-Jamming Scheme

Liu

et al. 2023

IEEE Trans. Wireless Commun.

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Providing quality communications under adversarial electronic attacks, e.g., broadband jamming attacks, is a challenging task. Unlike state-of-the-art approaches which treat jamming signals as destructive interference, this paper presents a novel active anti-jamming (AAJ) scheme for a jammed channel to enhance the communication quality between a transmitter node (TN) and receiver node (RN), where the TN actively exploits the jamming signal as a carrier to send messages. Specifically, the TN is equipped with a programmable-gain amplifier, which is capable of re-modulating the jamming signals for jamming modulation. Considering four typical jamming types, we derive both the bit error rates (BER) and the corresponding optimal detection thresholds of the AAJ scheme. The asymptotic performances of the AAJ scheme are discussed under the high jamming-to-noise ratio (JNR) and sampling rate cases. Our analysis shows that there exists a BER floor for sufficiently large JNR. Simulation results indicate that the proposed AAJ scheme allows the TN to communicate with the RN reliably even under extremely strong and/or broadband jamming. Additionally, we investigate the channel capacity of the proposed AAJ scheme and show that the channel capacity of the AAJ scheme outperforms that of the direct transmission when the JNR is relatively high.

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Section: A Jm Methodsmentioning

confidence: 99%

Jamming Modulation: An Active Anti-Jamming Scheme

Liu

et al. 2023

IEEE Trans. Wireless Commun.

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“…In such a condition, the transmitter up-converts the signal to the specified RF frequency band, while the received signal down-converts it to a 2.16 GHz IF band. The DVGA design reported in [16] with a 0.3 dB gain step using a 6-bit digital gain control is employed here. The optimization for bandwidth extension in [16] achieves a 3 dB bandwidth of more than 4 GHz.…”

Section: Fdd and Fd Modes Of Operationmentioning

confidence: 99%

“…The DVGA design reported in [16] with a 0.3 dB gain step using a 6-bit digital gain control is employed here. The optimization for bandwidth extension in [16] achieves a 3 dB bandwidth of more than 4 GHz. To cover all possible FDD operation bands, which satisfy the 802.11ad standard, the IFA requires a vast bandwidth of 6 GHz, centered from 12.096 GHz to 12.48 GHz, where the receiver works using channel 2 or channel 3, respectively, because the received IF signal may locate on either side of the IF LO with a 2.16 GHz carrier offset for those channels.…”

Section: Fdd and Fd Modes Of Operationmentioning

confidence: 99%

A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation

Wang,

Thangarasu,

Mahalingam

et al. 2024

Electronics

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This paper presents the design and measurement of an IEEE 802.11ad standard compatible RF transceiver for 60 GHz wireless communication systems. In addition to the traditional half-duplex (HD) mode, this work supports full-duplex (FD) operations to deliver better channel utilization and faster response times for the system. The isolation between the transmitter and receiver from the architecture design to system integration for FD operations has been fully considered. A digital self-interference cancellation (DSIC) is implemented in MATLAB to verify the FD performance. The super-heterodyne architecture with an intermediate frequency (IF) of 12 GHz is designed to suppress the image frequencies without using extra filters. A flexible phase-locked loop (PLL) synthesizer provides a local oscillator (LO) frequency with a 2 kHz resolution. Other than the time division duplex (TDD) mode used in the conventional 60 GHz system, a wide-bandwidth baseband digital variable-gain amplifier (DVGA) with a 3 dB bandwidth of more than 4 GHz also supports frequency division duplex (FDD) operations. The transceiver chip is fabricated using the Tower Jazz 0.18 µm SiGe BiCMOS process. With an on-board antenna, the transceiver covers all four channels in the 802.11ad standard, with MCS-12 (7.04 Gbps under 1.76 GSym/s and 16-QAM) under 1.5 m. In the proposed system design, the RF frontend-based self-interference (SI) suppression from the local transmitter to receiver LNA is around 54 dB. To achieve a practical FD application, the SI is further suppressed with the help of a digital SI compensation. The measured power consumption for the transmitter and receiver configurations are 194 mW and 231 mW, respectively, in HD mode and 398 mW for the FDD or FD operation mode.

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“…The VGA circuit topologies can be broadly classified into two categories based on the mode of gain tuning which are PGAs [7], [8], [9], [10], [11], [12], [13], [14], [15], [16] and analog-controlled VGAs [17], [18], [19], [20], [21], [22], [23], [24] . The most common technique used in the literature to achieve dB-linearity is through the pseudo-exponential behaviour of MOS transistors in the sub-threshold region.…”

Section: Introductionmentioning

confidence: 99%

A versatile programmable gain amplifier with wide dynamic range and low power consumption

Boora

Thangarasu

Yeo

2023

Preprint

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A tuneable gain analog amplifier is a primary building block in RF receivers specially to achieve high dynamic range. Here, we present a wide dB-linear gain range and low power programmable gain amplifier (PGA) fabricated in 40nm CMOS process, which exploits the exponential approximation of the MOS transistor in sub-threshold region. As a result, our PGA achieved one of the widest dB-linearity of 76 dB for 32 digital gain settings and a gain error of less than ± 0.5 dB and consumes only 167 µW of power from a 1.1 V supply. The proposed PGA has dual-mode gain tunability using analog voltage control and 5-bit digital control. At the maximum gain setting, the PGA exhibits a bandwidth of 1.1 MHz and output P1dB of -4.7 dBm. The PGA design is first of its kind attributing to its low-power consumption, wide dB-linear dynamic range, and dual-mode tunability. The novel design enables this PGA as a versatile and an effective block in RF integrated circuits.

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A 35-mW 30-dB Gain Control Range Current Mode Linear-in-Decibel Programmable Gain Amplifier With Bandwidth Enhancement

Cited by 19 publications

References 25 publications

Jamming Modulation: An Active Anti-Jamming Scheme

Jamming Modulation: An Active Anti-Jamming Scheme

A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation

A versatile programmable gain amplifier with wide dynamic range and low power consumption

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