A 33Mpixel CMOS imager with multi-functional 3-stage pipeline ADC for 480fps high-speed mode and 120fps low-noise mode

Yasue, Toshio; Tomioka, K.; Funatsu, Ryohei; Nakamura, Tomohiro; Yamasaki, Takahiro; Shimamoto, Hiroshi; Kosugi, Tadayoshi; Jun, Sung-Wook; Watanabe, Takashi; Nagase, Masanori; Toshiaki, Kitajima; Aoyama, Satoshi; Kawahito, Shoji

doi:10.1109/isscc.2018.8310198

Cited by 18 publications

(7 citation statements)

References 2 publications

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“…Power dissipation is a key specification in modern portable electronic devices. For those containing a digital camera, pipelined ADCs in the range of 8 to 12 bits are the type of data converter usually used [7]- [28]. So, several techniques have been developed to reduce the power dissipation in these types of circuits.…”

Section: Introductionmentioning

confidence: 99%

Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC

Díaz‐Madrid

Doménech‐Asensi

Martínez-Álvarez

et al. 2020

Circuits Syst Signal Process

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The power dissipation of a pipeline analog to digital converter (ADC) depends on different design strategies. In this brief communication, an 11-bit pipeline ADC consisting of five stages with 2.5 effective bit resolution is described. The circuit combines two main techniques to improve power dissipation, such as sharing OTAs between adjacent ADC stages and dynamic regulation of the OTA biasing according to the stage and subcycle of operation. To reduce the charge injection effect caused by the OTA sharing added circuitry, the ADC uses a topology based on four-input OTAs to reduce the number of transmission gates. The ADC has been fabricated using a standard 0.35 µm CMOS process. It consumes 17.85 mW at 10 MSample/s sampling rate. With this resolution and sampling rate, the measurement results show that it achieves 58.20 dB SNDR and 9.38 bit ENOB at 1 MHz input frequency.

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Section: Introductionmentioning

confidence: 99%

Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC

Díaz‐Madrid

Doménech‐Asensi

Martínez-Álvarez

et al. 2020

Circuits Syst Signal Process

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“…The rapid development of portable electronic devices using wireless data and video protocols has prompted the use of increasingly low‐power mixed signal circuits, specifically analog‐to‐digital converters (ADCs). Given these specifications, pipelined ADCs are popular architectures for high‐speed data conversion (10‐100 MS/s) at medium to high resolution (8‐14 bits) . They are employed in a variety of applications such as imaging or instrumentation systems.…”

Section: Introductionmentioning

confidence: 99%

“…Given these specifications, pipelined ADCs are popular architectures for high-speed data conversion (10-100 MS/s) at medium to high resolution (8-14 bits). 1 They are employed in a variety of applications such as imaging or instrumentation systems. Within this architecture, the first few stages have the greatest impact on the performances of the ADC, the comparator being one of their fundamental building blocks because their speed determines the time margin for settling the signal in the amplifying phase of the ADC.…”

Section: Introductionmentioning

confidence: 99%

A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

Diaz‐Madrid

Doménech‐Asensi

Hauer

et al. 2019

Engineering Reports

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This study presents a fully differential dynamic comparator with low kickback noise, an effect caused by voltage variations in the regeneration nodes of these types of circuit. Given their low power dissipation, dynamic comparators are key circuits in analog‐to‐digital converters (ADCs), especially in pipelined ADCs. The proposed comparator has been simulated and compared with three other comparator topologies. The value of the kickback noise generated by the proposed circuit is lower than that generated by other conventional dynamic comparators over a wide input range, while simultaneously showing a low offset voltage error. The dynamic comparator has been implemented in a low‐resolution ADC with a resolution of 2.5 effective bits, which has been prototyped in a 0.35‐μm CMOS AMS C35B4 process. Its size is 34 μm × 38 μm.

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“…To overcome this difficulty, we previously implemented a circuit topology with interleaved pixel source followers in a column CMS readout circuit [15]. In this architecture, the twopixel source followers work in parallel at different phases: the output of one is multiple sampled while settling the output of the other.…”

mentioning

confidence: 99%

“…This time-interleaved operation reduces the restriction imposed by the settling time of the pixel source followers and extends the time for multiple sampling. We applied this method to a column-parallel readout circuit in an 8K image sensor and achieved random noise of 3.2 e − at a readout time of 0.93 μs [8K 120 fps operation with digital correlated double sampling (CDS)] [15].…”

mentioning

confidence: 99%

Improved Correlated Multiple Sampling by Using Interleaved Pixel Source Follower for High-Resolution and High-Framerate CMOS Image Sensor

Tomioka¹,

Yasue²,

Funatsu³

et al. 2021

IEEE Trans. Electron Devices

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This article describes an improvement in the noise reduction performance of a column correlated multiple sampling (CMS) readout circuit using interleaved pixel source follower for high-resolution and high-framerate CMOS image sensors (CISs). In this architecture, the timeinterleaved operation of the two pixel source followers reduces the restrictions imposed by the settling time of the pixel source followers and extends the time for multiple sampling. The noise analysis indicates that this method has an advantage of enhanced noise reduction not only for thermal noise but also for 1/f noise when a high-speed readout operation is required. The measurement of the noise performance of the 8K image sensor using the CMS with the interleaved pixel source follower method exhibits a low input-referred noise of 3.2 e − at 8K 120 frames per second, while 4.6 e − with the conventional single-source follower readout method. The measurement results match reasonably well with the analysis presented in this article, demonstrating the effectiveness of the interleaved pixel source follower method for high-resolution and high-framerate CISs.Index Terms-8K, CMOS image sensor (CIS), correlated multiple sampling (CMS), high resolution, noise reduction. I. INTRODUCTIONT HE recent trends in video applications have tended toward increasing spatial resolutions, such as 4K, 8K, and high framerates. The video parameters of an ultrahighdefinition television (UHDTV) are standardized in recommendations ITU-R BT.

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A 33Mpixel CMOS imager with multi-functional 3-stage pipeline ADC for 480fps high-speed mode and 120fps low-noise mode

Cited by 18 publications

References 2 publications

Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC

Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC

A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

Improved Correlated Multiple Sampling by Using Interleaved Pixel Source Follower for High-Resolution and High-Framerate CMOS Image Sensor

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