A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

Abstract

This study presents a fully differential dynamic comparator with low kickback noise, an effect caused by voltage variations in the regeneration nodes of these types of circuit. Given their low power dissipation, dynamic comparators are key circuits in analog‐to‐digital converters (ADCs), especially in pipelined ADCs. The proposed comparator has been simulated and compared with three other comparator topologies. The value of the kickback noise generated by the proposed circuit is lower than that generated by other conventional dynamic comparators over a wide input range, while simultaneously showing a low offset voltage error. The dynamic comparator has been implemented in a low‐resolution ADC with a resolution of 2.5 effective bits, which has been prototyped in a 0.35‐μm CMOS AMS C35B4 process. Its size is 34 μm × 38 μm.

Design of a 0.4 V, 8.43 ENOB, 5.29 nW, 2 kS/s SAR ADC for Implantable Devices

“…However, as the gate to drain parasitic capacitance and a parallel combination of drain to bulk and source to bulk parasitic capacitance are associated with inputs in opposite directions, the difference of charge in these capacitances will add on to the input, thus producing a negligible amount of kickback noise. This has been verified by simulating the proposed design and the existing designs using the kickback noise test bench from [28], and the results are tabulated. Apart from saving power, this design also provides low offset, which is a key factor to enhance the performance of the comparator that, in turn, augments the performance of the whole ADC.…”

“…Because of their excellence in terms of achieving low power, some of the earlier works were also taken into consideration for comparison. The comparison proved that the proposed ADC has comparatively low power consumption, but [28] has the least. This is due to the fact that it is implemented using a power gating technique that reduces the leakage power; the same technique can be utilized in the proposed design to further enhance the power saving.…”

“…Apart from saving power, this design also provides low offset, which is a key factor to enhance the performance of the comparator that, in turn, augments the performance of the whole ADC. Process variations lead to device mismatches, which is a primary source of offset [28][29][30]. There are two types of offsets: static and dynamic, where static offset is due to current factor and threshold variations between the devices while dynamic offset is due to parasitic capacitance variations [22].…”

Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC

“…Moreover, the OTA includes a bias regulation circuitry which varies the amplifier biasing current according to the ADC subcycle of operation. In order to reduce the noise generated by the dynamic comparators, in this work comparators CMP1 and CMP2 used low kick-back noise circuits [10].…”

A complementary fully differential dynamic comparator with insensitive common-mode mismatch

“…To make the offset and power low, Gandhi [7] combines the advantages of Katyal's [8] and Min's [9] to propose a low-offset low-power structure. As for the kickback noise, based on Cho's [10], Diaz-Madrid [11] creates a structure to reduce it further. When considering setting a certain ratio between signals and references, the input signal range usually can not be too large.…”