A 33 V, 0.25 mΩ-cm/sup 2/ n-channel LDMOS in a 0.65 μm smart power technology for 20-30 V applications

Abstract

This paper describes a conventional 33V n-channel lateral DMOS (LDMOS) device integrated into a 20-30V 0.65pm (0.8pm minimum feiiture size) smart power technology based on an analog BiCMOS process flow. A specific onresistance of 0.25mQ-cm' has been reahzed for this device without significantly compromising the performance of other devices in the technology. This is the lowest specific on-resistance obtained to date for a power device in this voltage range.

Reliability assessment of integrated power transistors: Lateral DMOS versus vertical DMOS

“…In addition, for cost and reliability reasons, there is a continuous trend for integrating these transistors in the low voltage CMOS process instead of using discrete devices. Hence the so-called ''smart power technologies": technologies with a deep submicron core, embedded memory, and integrated power devices [5][6][7][8][9][10][11].…”

P-Channel Lateral Double-Diffused Metal–Oxide–Semiconductor Field-Effect Transistor with Split N-Type Buried Layer for High Breakdown Voltage and Low Specific On-Resistance

“…5,6) Many of these processes are developed from standard 5 V CMOS technologies by adding an N-type buried layer (NBL) before an epitaxial process for isolating a non grounded P-well from a P-substrate. [7][8][9][10] Owing to a heavily doped NBL, highbreakdown-voltage (BV dss ) devices exhibit P-well/NBL junction avalanche breakdown. To isolate two different potential P-wells effectively, NBL concentration should be sufficiently high to diffuse in order to link with N-wells.…”