A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme

Takemura, Riichiro; Kawahara, Takayuki; Miura, Katsuya; Yamamoto, Hiroyuki; Matsuzaki, N.; Ono, Ken; Yamanouchi, Michihiko; Ito, K.; Takahashi, Hiromasa; Ikeda, Shoji; Hasegawa, H.; Matsuoka, Hiroaki; Ohno, Hideo

doi:10.1109/jssc.2010.2040120

Cited by 120 publications

(50 citation statements)

References 7 publications

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“…Although the exact dimensions of the cell are layout-dependent, the size is dominated by the access transistor. The ratio of transistor width to cell width R = W T X /W cell can be as high as W T X / (W T X + F ), where F is the process feature size [20]. Reducing ∆ through free layer scaling can substantially reduce bit cell area and increase memory density as long as W T X is not reduced beyond F .…”

Section: B Relating Bit Cell Area To Thermal Stabilitymentioning

confidence: 99%

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Improving STT-MRAM density through multibit error correction

Bel

Kim

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-STT-MRAMs are prone to data corruption due to inadvertent bit flips. Traditional methods enhance robustness at the cost of area/energy by using larger cell sizes to improve the thermal stability of the MTJ cells. This paper employs multibit error correction with DRAM-style refreshing to mitigate errors and provides a methodology for determining the optimal level of correction. A detailed analysis demonstrates that the reduction in nonvolatility requirements afforded by strong error correction translates to significantly lower area for the memory array compared to simpler ECC schemes, even when accounting for the increased overhead of error correction.

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Section: B Relating Bit Cell Area To Thermal Stabilitymentioning

confidence: 99%

mentioning

confidence: 99%

Improving STT-MRAM density through multibit error correction

Bel

Kim

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

View full text Add to dashboard Cite

show abstract

“…[1][2][3] However, one goal in the development of p-STT-MRAMs beyond a feature size of 20 nm is to meet the demands of device performance, including a high tunneling magnetoresistance ratio (TMR) of 150%, a low critical current density (J C ) of 4.7 MA/cm 2 , and a good thermal stability (∆ = E/k B T) of 74. Here, E = K eff V is the energy barrier, M S is the saturation magnetization, H k is the anisotropy field, K eff is the effective perpendicular magnetic anisotropy (PMA) energy density, V is the volume of the magnetic layer, k B is the Boltzmann constant, and T is temperature.…”

Section: Introductionmentioning

confidence: 99%

Correlation between Pd metal thickness and thermally stable perpendicular magnetic anisotropy features in [Co/Pd]n multilayers at annealing temperatures up to 500 °C

Lee

Yang

et al. 2015

AIP Advances

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We examine highly stable perpendicular magnetic anisotropy (PMA) features of [Co/Pd]10 multilayers (MLs) versus Pd thickness at various ex-situ annealing temperatures. Thermally stable PMA characteristics were observed up to 500 °C, confirming the suitability of these systems for industrial applications at this temperature. Experimental observations suggest that the choice of equivalent Co and Pd layer thicknesses in a ML configuration ensures thermally stable PMA features, even at higher annealing temperatures. X-ray diffraction patterns and cross-sectional transmission electron microscopy images were obtained to determine thickness, post-annealing PMA behavior, and to explore the structural features that govern these findings.

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“…A number of nonvolatile integrated circuits where the magnetic tunnel junctions are embedded as a memory element have been demonstrated so far [4][5][6][7][8][9][10][11][12][13][14] .…”

Section: Introductionmentioning

confidence: 99%

MgO/CoFeB/Ta/CoFeB/MgO recording structure with low intrinsic critical current and high thermal stability

et al. 2014

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CoFeB-MgO based magnetic tunnel junctions with perpendicular easy axis are attracting much interest for application to nonvolatile very large scale integrated circuits. MgO/CoFeB/Ta/CoFeB/MgO recording structure with double-interface shows a high thermal stability factor without an increase of intrinsic critical current with comparison to MgO/CoFeB recording structure with single-interface. In this paper, we review our recent progress on the CoFeBMgO magnetic tunnel junctions with a double MgO barrier (MgO/CoFeB/Ta/CoFeB/MgO) recording structure. It enabled us to obtain magnetic tunnel junctions with a high thermal stability factor of 59 at a device dimension of 29 nm in diameter.

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A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme

Cited by 120 publications

References 7 publications

Improving STT-MRAM density through multibit error correction

Improving STT-MRAM density through multibit error correction

Correlation between Pd metal thickness and thermally stable perpendicular magnetic anisotropy features in [Co/Pd]n multilayers at annealing temperatures up to 500 °C

MgO/CoFeB/Ta/CoFeB/MgO recording structure with low intrinsic critical current and high thermal stability

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