A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor

Isobe, Atsuo; Tamura, Hikaru; Kimura, Kiyoshi; Ohmaru, Takuro; Uesugi, Wataru; Ishizu, Tomoko; Onuki, Tatsuya; Ohshima, Kazuaki; Matsuzaki, Takashi; Hirose, Atsushi; Suzuki, Yasutaka; Tsutsui, Naoaki; Atsumi, Tomoaki; Shionoiri, Yutaka; Goto, G.; Koyama, Jun; Fujita, Masahiro; Yamazaki, Shunpei

doi:10.1109/vlsic.2014.6858379

Cited by 12 publications

(7 citation statements)

References 1 publication

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“…10 We also reported a 32-bit processor with two-step, backup flipflops. 11 Moreover, we reported a combination with cache memory. 12 We have shrunk the technologies in the chip to broaden the CAAC-IGZO application areas.…”

Section: Hybrid Process Fabrication Structurementioning

confidence: 98%

Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor

et al. 2014

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Section: Hybrid Process Fabrication Structurementioning

confidence: 98%

Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor

et al. 2014

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“…This configuration demonstrates faster operation and lower power consumption than a conventional configuration in [28], as will be described in Section III-C. 2) Power Switch for Power Gating: As explained in Section II-A, Noff computing achieves low power consumption with fine-grained PG for each PLE. To implement fine-grained PG, a PLE uses the register shown in Fig.…”

Section: A Architecturementioning

confidence: 99%

“…Using a hybrid process technology that involves a CAAC-IGZO FET and CMOS FET, applications to large-scale integration (LSI), such as nonvolatile memory (nonvolatile oxide semiconductor RAM, NOSRAM) [19]- [22], CPUs [23]- [28], and an image sensor [29] have also been proposed. In such LSIs, the ultralow off-state current of a CAAC-IGZO FET is utilized effectively for nonvolatile memory cells [19]- [22], nonvolatile registers [23]- [28], and a charge retention node [29] with excellent charge retention characteristics.…”

Section: Introductionmentioning

confidence: 99%

Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register

Aoki

Okamoto

Nakagawa

et al. 2015

IEEE J. Solid-State Circuits

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Normally-off computing (Noff computing) using a multicontext field programmable gate array (MC-FPGA) consisting of crystalline oxide semiconductor FETs has been developed. The Noff computing discussed in this paper is a control architecture for an MC-FPGA capable of performing fine-grained power gating on each programmable logic element (PLE) whose registers include a volatile register and also a nonvolatile shadow register for storing and loading data in the volatile register. The MC-FPGA performs fine-grained control of power supplied only to PLEs contributing to effective calculation, when context switching happens. With an MC-FPGA fabricated with a hybrid process of a 1.0 µm crystalline oxide semiconductor FET on a 0.5 µm CMOS FET, it has been confirmed that the proposed Noff computing can resume the previous task when a context switches back to it, increases PLE use efficiency, and reduces the power consumption by 27.7% at operating frequencies of 20 MHz with a driving voltage of 2.5 V.Index Terms-CAAC-IGZO, crystalline IGZO, crystalline oxide semiconductor, field programmable gate array, multicontext, nonvolatile memory, normally-off computing, oxide semiconductor, power gating, shadow register. 0018-9200

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“…For example, displays [12]- [15], large scale integrations such as memories [16]- [20], CPUs [21]- [26], and FPGAs [1], [2], [27]- [31], and image sensors [32]- [36] have been reported to exhibit a variety of features that can be achieved with CAAC-IGZO FETs, e.g., low power consumption and additional functions owing to the ultralow leakage. A multicontext (MC) FPGA that includes nonvolatile configuration memory with a CAAC-IGZO FET (CAAC-IGZO FPGA) [1], [2], [27]- [31] features the following characteristics: 1) fine-grained power gating (PG) [27] capable of controlling power supply to individual PLEs; 2) MC architecture [28] capable of fast configuration switching; 3) data load/store between a volatile register and its dedicated nonvolatile shadow register before and after power shutoff by fine-grained PG [29]; 4) normally OFF driving [29] to support these functions.…”

Section: Introductionmentioning

confidence: 99%

Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch

Kozuma

Okamoto

Nakagawa

et al. 2017

IEEE Trans. VLSI Syst.

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A field-programmable gate array (FPGA) using a crystalline oxide semiconductor of c-axis-aligned crystal indium-gallium-zinc oxide (CAAC-IGZO) has been developed, which is capable of subthreshold operation used for energy harvesting. To achieve subthreshold operation, the CAAC-IGZO FPGA has a structure designed as an extension of a boosting pass gate using a CAAC-IGZO FET and employs overdriving of a programmable routing switch and a programmable power switch for power gating (PG). A CAAC-IGZO FET is used to give an ideal floating gate with excellent charge retention. A chip fabricated using a 0.8-µm CAAC-IGZO/ 0.18-µm CMOS hybrid process achieves subthreshold operation while maintaining the features required for normally off computing proposed in our previous study. Specifically, these features are realized by fine-grained PG for individual programmable logic elements (PLEs), fast configuration switching between contexts, and load/store between a volatile register and a nonvolatile shadow register in the PLEs. The chip operation at a minimum operating voltage of 180 mV with a combinational circuit configuration is demonstrated. With a sequential circuit configuration, the chip operates at a minimum operating voltage of 190 mV with 12.5 kHz, and the minimum power-delay product is 3.40 pJ/operation at 330 mV.Index Terms-c-axis-aligned crystal indium-gallium-zinc oxide (CAAC-IGZO), crystalline oxide semiconductor, fieldprogrammable gate array (FPGA), low voltage, multicontext (MC), nonvolatile memory, nonvolatile shadow register, normally OFF computing, power gating (PG), subthreshold operation.

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A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor

Cited by 12 publications

References 1 publication

Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor

Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor

Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register

Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch

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