A 300‐mA load CMOS low‐dropout regulator without an external capacitor for SoC and embedded applications

Huang, Shanzhou; Duan, Quanzhen; Guo, Tian; Cheng, Yaping; Yin, Jiaqi; Ding, Yuemin

doi:10.1002/cta.2356

Cited by 13 publications

(9 citation statements)

References 17 publications

(45 reference statements)

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“…Academic research works [6] can achieve low dropout voltage, but [6] does not provide the data of V OUT when I OUT is smaller than 30 mA. Also, all of these academic research works including [6], [15] and [7] do not consider the wide temperature operation and package. Finally, Figure of Merit (FOM) are compared by using [6]:…”

Section: Measurement Resultsmentioning

confidence: 99%

An External Capacitor-Less Low-Dropout Voltage Regulator Using a Transconductance Amplifier

Fan

Diao²,

Li³

et al. 2019

IEEE Trans. Circuits Syst. II

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This paper presents an external capacitor-less NMOS low-dropout (LDO) voltage regulator integrated with a standard CSMC 0.6 µm BiCMOS technology. Over a −55 • C to +125 • C temperature range, the fabricated LDO provides a stable and considerable amount of 3 A output current over wide ranges of output capacitance C OUT (from zero to hundreds of µF) and effective-series-resistance (ESR) (from tens of milliohms to several ohms). A low dropout voltage of 200 mV has been realised by accurate modelling. Operating with an input voltage ranging from 2.2 V to 5.5 V provides a scalable output voltage from 0.8 V to 3.6 V. When the load current jumps from 100 mA to 3 A within 3 µs, the output voltage overshoot remains as low as 50 mV without output capacitance, C OUT. The system bandwidth is about 2 MHz, and hardly changes with load altering to ensure system stability. To improve the load transient response and driving capacity of the NMOS power transistor, a buffer with high input impedance and low output impedance is applied between the transconductance amplifier and the NMOS power transistor. The total area of fabricated LDO voltage regulator chip including pads is 2.1 mm×2.2 mm.

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Section: Measurement Resultsmentioning

confidence: 99%

An External Capacitor-Less Low-Dropout Voltage Regulator Using a Transconductance Amplifier

Fan

Diao²,

Li³

et al. 2019

IEEE Trans. Circuits Syst. II

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“…The external ESR and output off-chip capacitor (C o ) generated a third LHP zero to compensate for the negative phase shift caused by the low-frequency nondominant pole [20]. Consequently, four poles and three LHP zeros were generated in the loop of the linear regulator core.…”

Section: The Core Linear Regulatormentioning

confidence: 99%

A Two-Module Linear Regulator with 3.9–10 V Input, 2.5 V Output, and 500 mA Load

Duan

Huang

et al. 2019

Electronics

Self Cite

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A linear regulator with an input range of 3.9–10 V, 2.5 V output, and a maximal 500 mA load for use with battery systems was developed and presented here. The linear regulator featured two modules of a preregulator and a linear regulator core circuit, offering minimized power dissipation and high-level stability. The preregulator delivered an internal power voltage of 3 V and supplied internal circuits including the second module (the linear regulator core). The preregulator fitted with an active, low-pass filter provided a low-noise reference voltage to the linear regulator core circuit. To ensure operational stability for the linear regulator, error amplifiers incorporating the Miller compensation technique and featuring a large slewing rate were employed in the two modules. The circuit was successfully implemented in a 0.25 µm, 5 V complementary metal-oxide semiconductor (CMOS) process featuring 20 V drain-extended MOS (DMOS)/bipolar high-voltage devices. The total silicon area, including all pads, was approximately 1.67 mm2. To reduce chip area, bipolar rather than DMOS transistors served as the power transistors. Measured results demonstrated that the designed linear regulator was able to operate at an input voltage ranging from 3.9 to 10 V and offer a maximum 500 mA load current with fixed 2.5 V output voltage.

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“…Furthermore, low-cost, compact size, reducing the number of power/ground pins, 1 provision of different power rails, 2 and fast transient response due to high switching frequency operation make FIVR suitable for portable systems, Internet of Things (IoT), System on Chip (SoC), mobile phone, smart watch, implantable biomedical applications, wireless sensors, and energy harvesting applications. [3][4][5][6][7][8] Implementing a power supply using both off-chip and on-chip technologies together (hybrid power supply) is a suitable way to supply the required power of high-performance VLSI systems. 9,10 In an off-chip voltage regulator, first, the voltage step-down is performed to obtain an intermediate voltage level.…”

Section: Introductionmentioning

confidence: 99%

“…Using the DVFS technique for an electronic system requires a large number of FIVRs, each of which supplies the voltage of a core or a block independently and with the aim of increasing the system efficiency. Furthermore, low‐cost, compact size, reducing the number of power/ground pins, 1 provision of different power rails, 2 and fast transient response due to high switching frequency operation make FIVR suitable for portable systems, Internet of Things (IoT), System on Chip (SoC), mobile phone, smart watch, implantable biomedical applications, wireless sensors, and energy harvesting applications 3–8 …”

Section: Introductionmentioning

confidence: 99%

Fully integrated switched‐inductor switched‐capacitor dual‐path DC–DC converter

Meshkat

Dehghani

Farzanehfard

2022

Circuit Theory & Apps

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A fully integrated switched-inductor switched-capacitor (SISC) DC-DC converter is proposed. This converter is designed in such a way that the input voltage can be twice the process allowable voltage without damaging the on-chip transistors. To mitigate large series resistance of on-chip inductors as one of the main challenges in the switched-inductor power supply on chip, two solutions are proposed. By using analytical model of an on-chip inductor, optimal physical dimensions are designed to achieve the desired inductance with minimum series resistance in a small area. Along with the optimization, the dualpath structure of the proposed converter reduces series resistance losses of the on-chip inductor and increases the effective quality factor up to 7 times in duty cycle of 0.8. The proposed converter is implemented in 0.18 μm standard CMOS process. The circuit converts input voltage of 3.6-0.9 V at the load current of 125 mA with the efficiency of 72.8%. Efficiency enhancement factor reaches 72% at 600 mV output voltage. The achieved current density of the proposed converter is 333 mA/mm 2 . By calculating small signal model of the proposed converter and designing a suitable feedback loop, an appropriate transient behavior was provedcascode buck converter, fully integrated voltage regulator, high current density, high stepdown, inductor quality factor boosting, on-chip inductor optimum design

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A 300‐mA load CMOS low‐dropout regulator without an external capacitor for SoC and embedded applications

Cited by 13 publications

References 17 publications

An External Capacitor-Less Low-Dropout Voltage Regulator Using a Transconductance Amplifier

An External Capacitor-Less Low-Dropout Voltage Regulator Using a Transconductance Amplifier

A Two-Module Linear Regulator with 3.9–10 V Input, 2.5 V Output, and 500 mA Load

Fully integrated switched‐inductor switched‐capacitor dual‐path DC–DC converter

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