A 3.96 GHz phase-locked loop for mode-1 MB-OFDM UWB hopping carrier generation

Yongzheng, Zheng; Li, Weinan; Xia, Ling; Huang, Yumei; Hong, Zhiliang

doi:10.1088/1674-4926/30/7/075003

Cited by 2 publications

(1 citation statement)

References 9 publications

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“…c D 50 kHz, and phase margin P D 50 ı , according to Ref. [22], and the parameters of the loop filter are summarized as C…”

Section: Pfd Cp and Lpfmentioning

confidence: 99%

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

Li¹,

Zhang²,

Li³

et al. 2011

J. Semicond.

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A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18 m CMOS technology. A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance. A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature (I/Q) local oscillating signal. A high-speed 8/9 dual-modulus prescaler (DMP), a programmable-delay phase frequency detector without dead-zone problem, and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz, and the phase noise is -98.53 dBc/Hz at 100-kHz offset and -121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power supply. The total area of the receiver is 2.4 1.6 mm 2 .

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“…c D 50 kHz, and phase margin P D 50 ı , according to Ref. [22], and the parameters of the loop filter are summarized as C…”

Section: Pfd Cp and Lpfmentioning

confidence: 99%

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

Li¹,

Zhang²,

Li³

et al. 2011

J. Semicond.

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show abstract

A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology

Talwekar¹,

Limaye²

2012

VLSICS

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A high speed low power consumption positive edge triggered Delayed (D) flip-flop was designed for increasing the speed of counter in Phase locked loop, using 180 nm CMOS technology. The designed counter has been used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The proposed circuit is faster than conventional circuit as it has fast reset operation. The circuit consumes less power as it prevents short circuit power consumption. The circuit operates at 1.8V power supply. This work has been used in the design. of 2.4 GHz CMOS PLL targeting OFDM application. The CMOS based fast D-ff circuit has designed and simulated by Virtuoso tool of CADENCE spectre KEYWORDS

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A 3.96 GHz phase-locked loop for mode-1 MB-OFDM UWB hopping carrier generation

Cited by 2 publications

References 9 publications

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology

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