A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology

Talwekar, R. H.; Limaye, S. S.

doi:10.5121/vlsic.2012.3513

Cited by 3 publications

(2 citation statements)

References 4 publications

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“…The reset pass delay of PFD should be short enough. In this work, a TSPC D flipflop based PFD with a NOR gate in reset pass utilized in order to short reset time [12][13][14]. At charge pump, static and dynamic errors due to non-ideal effects of transistors were reduced using axillary switches in parallel with main switches.…”

Section: Pfd/cp/lpfmentioning

confidence: 99%

A Fast Settling Multi-Standard CMOS Fractional-N Frequency Synthesizer for DECT/GSM/ CDMA &/NADC Wireless Communication Standards

Yargholi

Vali

2020

sjis

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A fast settling multi-standard CMOS fractional-N frequency synthesizer for DECT, GSM, CDMA and NADC wireless communication standards is proposed. This frequency synthesizer was simulated with ADS2008 in TSMC RF CMOS 0.18 µm. Frequency range is 824-1900 MHz, a switched capacitor LC-VCO was used in order to produce this frequency range. Frequency synthesizers have three main specifications of phase noise, settling time and power consumption. A new channel select circuit was designed instead of ∑∆ modulator to locate spur tones far from center frequency. A high reference frequency was used in order to reduce the VCO phase noise and locate the spur tones far from center frequency; these tones are produced by charge pump (reference spur) and N/N+1 divider (fractional spur). Two ways were used for phase noise optimization; in the first way phase noise was reduced by a low pass filter and a bypass capacitor (CT) that eliminate thermal noise and 2ω0 harmonics of tail current source; in the second way with biasing of VCO transistors only in saturation region preventing reduction of quality factor(Q) in tank circuit. These two ways in VCO of DECT were used, consequently the phase noise at 1875MHz center frequency was improved from -119.4 dBc/Hz at 3.4 MHz offset frequency to -144.3 dBc/Hz at 3.4 MHz offset frequency. The settling time for all standards was achieved less than almost 1 μs over the entire frequency range. For DECT synthesizer phase noise of -116.37 dBc/Hz at 3 MHz offset frequency was obtained, the first spur tone was located in 7.35 MHz offset from center frequency, also settling time of 350ns was obtained. The whole frequency synthesizer in loop1 (for DECT) draws 13 mA and in loop2 (for GSM900, CDMA & NADC) draws 13.67 mA from a 1.8 V voltage supply.

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Section: Pfd/cp/lpfmentioning

confidence: 99%

A Fast Settling Multi-Standard CMOS Fractional-N Frequency Synthesizer for DECT/GSM/ CDMA &/NADC Wireless Communication Standards

Yargholi

Vali

2020

sjis

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“…A PFD is a key sub‐circuit to the operation of a PLL. The purpose of a PFD is to compare two periodic input signals and generate output pulses indicative of the phase and frequency difference of the two periodic input signals [1]. Conventional PFDs are designed by using D flip‐flops with a reset path as feedback loop.…”

Section: Introductionmentioning

confidence: 99%

Simple high‐resolution CMOS phase frequency detector

2015

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A high-resolution phase frequency detector (PFD) is designed for highfrequency signal detection and low jitter phase locked loop applications. The proposed PFD eliminates the reset path delay and usage of any latches, minimise the dead zone to near zero by generating narrow pulses at each input rising edge. In addition, the designed PFD completely removes unwanted output glitches, accepts inputs with a large difference in frequency, and also has the ability to drive a large capacitive load with minimal impact on performance. The proposed PFD is designed in 90 nm CMOS technology with a 1.2 V power supply. Simulation results indicate that the proposed design can operate over a wide range of frequencies from 10 kHz to 6 GHz and can detect phase differences for inputs as small as 125 fs for all frequencies of operation and for all process corners. The simulated power consumption is 75 µW at 166.6 MHz with an input phase difference of 125 fs.Introduction: Phase frequency detectors (PFDs) are widely used in micro-electronic circuit designs including phase locked loops (PLLs), radars, and interferometers. A PFD is a key sub-circuit to the operation of a PLL. The purpose of a PFD is to compare two periodic input signals and generate output pulses indicative of the phase and frequency difference of the two periodic input signals [1]. Conventional PFDs are designed by using D flip-flops with a reset path as feedback loop. This conventional PFD has the drawbacks of high power consumption, large dead zone, limited operating speed, and undesired output glitches [2]. Improved design topologies manage to reduce dead-zone errors [3] to 15 ps and attempt to simplify design circuitry. Pass transistor-based logic PFD [4] designs try to minimise the number of transistors to improve performance benchmarks, but such designs are subjected to output voltage drops and performance is affected greatly by adding output load capacitance. An alternative flip-flop-based design [5] has been proposed to reduce the dead-zone error to near 750 fs, but it has a drawback of large power consumption and moderate operating frequency due to its circuit complexity and long critical path. The dead zone is defined as the minimum bound of phase error where PFD is unable to detect the difference in input phase. Therefore, the dead zone plays an important role in the operation of a PFD since dead-zone errors introduce jitter to PLL devices [6].In this Letter, a new design topology without any feedback path is presented to improve dead zone of the PFD while simplifying the design to reduce power consumption. The proposed PFD design accepts two input phase differences over the complete range [0, 2π]. The output glitches are completely removed and this PFD can drive large capacitive loads without affecting its normal operation. Dead-zone error of the PFD design is reduced to almost zero by removing the reset path.

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Design and implementation of 1 GHz Current Starved Voltage Controlled Oscillator (VCO) for PLL using 90nm CMOS technology

Muddi

Shinde

Shivaprasad

2015

2015 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)

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A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology

Cited by 3 publications

References 4 publications

A Fast Settling Multi-Standard CMOS Fractional-N Frequency Synthesizer for DECT/GSM/ CDMA &/NADC Wireless Communication Standards

A Fast Settling Multi-Standard CMOS Fractional-N Frequency Synthesizer for DECT/GSM/ CDMA &/NADC Wireless Communication Standards

Simple high‐resolution CMOS phase frequency detector

Design and implementation of 1 GHz Current Starved Voltage Controlled Oscillator (VCO) for PLL using 90nm CMOS technology

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