A 3.5 GHz CMOS Doherty power amplifier with integrated diode linearizer targeted for WiMax applications

Cui, Xian; Roblin, Patrick; Lee, Jong-Soo; Liou, Wan–Rone; Kim, Young Gi

doi:10.1109/mwscas.2007.4488629

Cited by 9 publications

(1 citation statement)

References 7 publications

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“…Both designed DPAs are summarized and compared to the target specifications in Table 3.7. (Cui, Roblin et al, 2007) 0.18 μm CMOS 3.7 3.5 24.4 36.1 6 (Ryu, Jung & Jeong, 2012) (Kim, Son et al, 2014) 0.18 μm CMOS -0.89 25 43.6 5 (Ryu, Jang et al, 2014) 0 The designed DPA parameters are summarized and compared to those presented in the similar CMOS process scale in Table 3.8. Both designed DPA configurations are on par with the published DPAs, but is designed to operate at a much higher 6.5 GHz frequency with a smaller supply voltage.…”

Section: Classical and Simplified Doherty Power Amplifier Configuratimentioning

confidence: 99%

Mid-band 5G wireless network power amplifier research

Vasjanov¹

2019

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Vilnius 2019 Disertacija rengta 2015-2019 metais Vilniaus Gedimino technikos universitete. Vadovas doc. dr. Vaidotas BARZDĖNAS (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija-T 001). Vilniaus Gedimino technikos universiteto Elektros ir elektronikos inžinerijos mokslo krypties disertacijos gynimo taryba: Pirmininkas prof. habil. dr. Romualdas NAVICKAS (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija-T 001). Nariai: dr. Alvydas LISAUSKAS (Lenkijos mokslų akademijos Aukšto slėgio fizikos institutas, fizika-N 002), doc. dr. Vitalij NOVICKIJ (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija-T 001), prof. dr. Šarūnas PAULIKAS (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija-T 001), prof. dr. Algimantas VALINEVIČIUS (Kauno technologijos universitetas, elektros ir elektronikos inžinerija-T 001). Disertacija bus ginama viešame Elektros ir elektronikos inžinerijos mokslo krypties disertacijos gynimo tarybos posėdyje 2019 m. birželio 13 d. 10 val. Vilniaus Gedimino technikos universiteto senato posėdžių salėje.

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Section: Classical and Simplified Doherty Power Amplifier Configuratimentioning

confidence: 99%

Mid-band 5G wireless network power amplifier research

Vasjanov¹

2019

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2.4 GHz Doherty power amplifier with on-chip active balun design

Qi-rong

Shi

2009

2009 IEEE 8th International Conference on ASIC

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In this work, a 2.4 GHz Doherty power amplifier with a on-chip active balun is presented by using the SMIC CMOS O.l Sum technology. With the employment of this balun, the bulky input quadrature coupler which is needed in the traditional Doherty power amplifier could be canceled. Consequently, the power gain ofthe Doherty power amplifier is substantially improved For there is only one DC path in this designed on-chip active balun, the DC power consumption is very low. As far as the author has known, it is the first time that this low DC consumption blaun has been reported to be used in the Doherty power amplifier. The maximum output power of this amplifier is 22.4dBm with its power added efficiency as 47.6% . At i-dB compression point this PA exhibits 2i.3dBm of output power with 45% PAE with 20dB ofpower gain.Index Terms -CMOS, Doherty power amplifier (PA), high-efficiency amplifier, Balun I.

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