A 3.3mW 12MS/s 10b pipelined ADC in 90nm digital CMOS

Wang, R.; Martin, Kenneth W.; Johns, D.A.; Burra, G.

doi:10.1109/isscc.2005.1493977

Cited by 21 publications

(8 citation statements)

References 3 publications

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“…The ADC reaches a FOM of 0.22 pJ/step. As a reference, Table 2 shows a comparison of this work and some other ADCs [1,2,4,8]. This design achieves the best FOM in this category.…”

Section: Resultsmentioning

confidence: 99%

“…Pipelined ADCs are widely used for communication and video applications which require tens-of-MHz conversion rate, low latency and medium resolution [1][2][3][4]. For embedded applications, an ADC is especially concerned with its power efficiency.…”

Section: Introductionmentioning

confidence: 99%

“…Simulation results show that the proposed scheme improves the SFDR by about 3 dB. For the 1.2-V supply voltage, a two-stage amplifier is adopted to maintain the ADC performance [2], and a hybrid compensation method is proposed to achieve high bandwidth and enough phase margin (PM) with low power dissipation.…”

Section: Introductionmentioning

confidence: 99%

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A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter

Shu¹,

Guo²,

Ren

et al. 2011

Analog Integr Circ Sig Process

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This paper presents a 10-bit 40-MS/s pipelined analog-to-digital converter (ADC) in a 0.13-lm CMOS process for subsampling applications. A simplified opampsharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency compensation is developed to achieve both high bandwidth and large swing with low power dissipation. The measured result shows that the ADC achieves over 77 dB spurious free dynamic range (SFDR) and 57.3 dB signal-to-noiseplus-distortion ratio (SNDR) within the first Nyquist zone and maintains over 70 dB SFDR and 55.3 dB SNDR for input signal up to 75 MHz. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.2 LSB and ±0.3 LSB, respectively. The ADC consumes 15.6 mW at the sampling rate of 40 MHz from a 1.2-V supply voltage, and achieves a figure-of-merit (FOM) value of 0.22 pJ per conversion step.

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“…The ADC reaches a FOM of 0.22 pJ/step. As a reference, Table 2 shows a comparison of this work and some other ADCs [1,2,4,8]. This design achieves the best FOM in this category.…”

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter

Shu¹,

Guo²,

Ren

et al. 2011

Analog Integr Circ Sig Process

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show abstract

“…So the design target is a low power high-performance CMOS ADC, of which the resolution is Among various ADC architectures, pipelined converters could provide a good tradeoff between the performance and power consumption. Recently reported results also indicate that the pipeline architecture is cost-efficient [3] and suitable for the deep sub-micrometer digital CMOS technologies [4,5].…”

Section: Adc Architecturementioning

confidence: 99%

Design of an ADC for subsampling video applications

Zeng

Zhang

et al. 2006

Analog Integr Circ Sig Process

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This paper describes a 10 bit 30 Msample/s (MSPS) CMOS analog-to-digital converter (ADC) for highspeed signal processing, especially for subsampling applications, for example digital video broadcasting over cable (DVB-C), terrestrial (DVB-T) and handheld (DVB-H) systems. The proposed pipelined ADC shows a good figure-ofmerit (FoM). It adopts a power efficient amplifier sharing technique, a symmetrical gate-bootstrapping technique with modified timing for the bottom-sampling switch of a wideband sample-and-hold (S/H) circuit, a proposed stable highswing bias circuit for a wide-swing gain-boosting telescopic amplifier. The measured differential and integral nonlinearities of the prototype in a 0.25-µm CMOS technology show less than 0.4 least significant bit (LSB) and 0.85 LSB respectively at full sampling rate. The ADC exhibits higher than 9 effective number of bits (ENOB) for input frequencies up to about 60 MHz, which is the fourfold Nyquist rate (fs/2), at 30 MSPS. The ADC consumes 60 mW from a 3-V supply and occupies about 1.36 mm 2 .

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“…Most of the previously reported 10 b ADCs with similar specifications are based on single-bit-per-stage or multi-bit-per-stage pipeline architectures with more than four stages [1][2][3]. Increasing the number of pipeline stages allows high-speed operation to be achieved due to the reduced amplifier gain and small load capacitance resulting from the decreased physical size of the residue amplifiers and sampling capacitors at the expense of increased power consumption and chip area due to the increase in the number of inter-stage amplifiers.…”

mentioning

confidence: 99%

A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched‐bias power‐reduction techniques

Choi

Kim

Lee

et al. 2008

Circuit Theory & Apps

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SUMMARYThis paper proposes a 10 b 25 MS/s 4.8 mW 0.13 m CMOS analog-to-digital converter (ADC) for highperformance portable wireless communication systems, such as digital video broadcasting, digital audio broadcasting, and digital multimedia broadcasting (DMB) systems, simultaneously requiring a low-voltage, low-power, and small chip area. A two-stage pipeline architecture optimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate, while switched-bias power-reduction techniques reduce the power consumption of the power-hungry analog amplifiers. Lownoise reference currents and voltages are implemented on chip with optional off-chip voltage references for low-power system-on-a-chip applications. An optional down-sampling clock signal selects a sampling rate of 25 or 10 MS/s depending on applications in order to further reduce the power dissipation. The prototype ADC fabricated in a 0.13 m 1P8M CMOS technology demonstrates a measured peak differential non-linearity and integral non-linearity within 0.42 LSB and 0.91 LSB and shows a maximum signal-tonoise-and-distortion ratio and spurious-free dynamic range of 56 and 65 dB at all sampling frequencies up to 25 MHz, respectively. The ADC with an active die area of 0.8mm 2 consumes 4.8 and 2.4 mW at 25 and 10 MS/s, respectively, with a 1.2 V supply.

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A 3.3mW 12MS/s 10b pipelined ADC in 90nm digital CMOS

Cited by 21 publications

References 3 publications

A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter

A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter

Design of an ADC for subsampling video applications

A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched‐bias power‐reduction techniques

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