A 2v-supply Voltage 16Mb Sram Cell With Load-lock-CVD Poly And DCS-WSix Technologies

Kawarnura,; Satô,; Hakozaki,; Nakano, Mikio; Tateyama,; Hayashida,; Yamazaki,; Ohnishi,; Iguchi,; Sakiyama,

doi:10.1109/vlsit.1993.760248

Cited by 2 publications

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“…Figure 1 shows the comparison of the SRAM cell size in MCU and SOC products. [3][4][5] In the same process generation, the SRAM cell size of MCU is larger than that of SOC because the thermal budget for the SG-MONOS is considered in addition to gate oxide reliability requirements such as time-dependent dielectric breakdown and negative bias temperature instability. However, with the progress of process scaling, the difference in SRAM cell size between SOC and MCU products has become small.…”

Section: Introductionmentioning

confidence: 99%

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

Okamoto

Maekawa

Kawashima

et al. 2015

Jpn. J. Appl. Phys.

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High quality static random access memory (SRAM) for 40-nm embedded MONOS flash memory with split gate (SG-MONOS) was developed. Marginal failure, which results in threshold voltage/drain current tailing and outliers of SRAM transistors, occurs when using a conventional SRAM structure. These phenomena can be explained by not only gate depletion but also partial depletion and percolation path formation in the MOS channel. A stacked poly-Si gate structure can suppress these phenomena and achieve high quality SRAM without any defects in the 6σ level and with high affinity to the 40-nm SG-MONOS process was developed.

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Section: Introductionmentioning

confidence: 99%

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

Okamoto

Maekawa

Kawashima

et al. 2015

Jpn. J. Appl. Phys.

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A new toroidal TFT structure for future generation SRAMs

Hayden

Cooper

Roth³

et al.

Proceedings of IEEE International Electron Devices Meeting

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A new toroidal TFT structure has been developed for future generation SRAM products. This new TFT provides excellent device performance at scaled power supply voltages and offers significant savings in bitcell area.Thin film polysilicon transistors (TFTs) are used as bitcell loads in many 4Mb products and in all 16Mb SRAM products reported to date [l-81. It is believed that they will be required for all future generations of SRAM products [9]. Polysilicon resistors have reached their scaling limit as loads in SRAM bitcells [lo]. TFTs are now required to 1) simultaneously meet standby current requirements and compensate for stray bitcell leakages, and 2) improve SER (soft error rate) by increasing both cell capacitance and stored voltage levels, and hence the stored charge. In scaling to future technologies, reducing bitcell area is of ever increasing difficulty. There is a growing trend towards three dimensional structures, such as trench MOSFETs [ l l ] and self-aligned contacts, in an attempt to reduce the area required for placing four MOSFETs and the required interconnections in bulk silicon. With reducing the cell's silicon footprint, the difficulty of including TFTs in the bitcell increases. TFTs in SRAM bitcells typically require a gate length approximately twice the minimum feature size plus a gate-to-drain offset on the order of a feature size in order to ensure adequate device characteristics. The sourceldrain regions must be separated far enough to compensate'for rapid diffusion of boron in polysilicon and to ensure acceptable short channel behavior. Also, a sufficient gate-to-drain offset is required to minimize offcurrent by lowering the drain electric field and hence reducing the field emission related grain boundary leakage current.In this paper, a new TFT structure has been developed which provides excellent TFT characteristics while minimizing layout area. This TFT is built as a 'spacer' inside of a hole or contact-like feature. The TFT channel lines this hole, much like a donut or toroid, hence, a 'toroidal TFT'. The channel is connected to the source and drain by etching through the appropriate polysilicon lines and forming polysilicon sidewall contacts [3]. The TFT gate is formed by depositing and patterning a polysilicon layer over the toroidal shaped channel region. Other variations of this structure are possible, such as a pillar rather than a hole to suppo! -l the toroid. Because the TFT channel is formed around the circumference of a circular feature, the gated channel length is increased by a factor of n/2 or approximate 57%. A very thin TFT channel can be easily formed using conventional processing. This ensures the channel will be fully depleted even at lowered power supply voltages, thus providing improved device performance. A schematic cross-section of the toroidal TFT structure is presented in Figure-1, as well as a potential layout.The toroidal TFT structure was fabricated by modifying an existing 16Mb BiCMOS SRAM process [6]. The process flow is presented schematically in Figure ...

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A 2v-supply Voltage 16Mb Sram Cell With Load-lock-CVD Poly And DCS-WSix Technologies

Cited by 2 publications

References 0 publications

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

A new toroidal TFT structure for future generation SRAMs

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