A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor

Chun, Ki Chul; Zhang, Wei; Jain, Pulkit; Kim, C. H.

doi:10.1109/jssc.2012.2206685

Cited by 37 publications

(22 citation statements)

References 14 publications

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“…As mentioned above, the DRT of a 2T Gain-Cell suffers from significant variations, both global and local, as has been well documented and demonstrated in previous publications [2]- [4], including recent measurements by the authors [7]. However, the replica mechanisms described above are only designed to track the global variations and access statistics of the array.…”

Section: B Replica Technique Conceptmentioning

confidence: 85%

“…All of these factors are significantly affected by both environmental and manufacturing variations, as demonstrated in measurements by [3]. This results in a large spread of DRT distribution [2], [7], and as with any memory array, necessitates design for the worst cell. However, in addition to the effects of PVT variations, SN leakage currents are highly sensitive to the biasing level of WBL.…”

Section: Replica Technique For Auto-refresh Timing a Retention Tmentioning

confidence: 99%

“…2. A total of 32 replica cells were placed in an additional column to deal with the large distribution of local variations [2]. These cells are driven low upon the assertion of the external RefreshReplica signal within a single cycle, independent of the operation of the rest of the array.…”

Section: Replica Technique Integration Into Gain Cell Arraymentioning

confidence: 99%

“…The majority of the target applications for such memories have been large caches that benefit from the reduced transistor count of gain cells (GCs) [1], [2], [8]. However, several groups have shown the potential for integration of GC-eDRAM as a candidate for the replacement of SRAM in ultra-low power (ULP) applications [3]- [7], [9].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

Teman

Meinerzhagen

Giterman

et al. 2014

IEEE Trans. Circuits Syst. II

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Abstract-Gain cells have recently been shown to be a viable alternative to SRAM in low-power applications due to their low leakage currents and high density. The primary component of power consumption in these arrays is the dynamic power consumed during periodic refresh operations. Refresh timing is traditionally set according to a worst-case evaluation of retention time, under extreme process variations and worst-case access statistics, leading to frequent, power hungry refresh cycles. In this paper, we present a replica technique for automatically tracking the retention time of a gain cell embedded DRAM macrocell according to process variations and operating statistics, thereby reducing the data retention power of the array. A 2 kb array was designed and fabricated in a mature 0.18µm CMOS process, appropriate for integration in ultra-low power applications, such as biomedical sensors. Measurements show efficient retention time tracking across a range of supply voltages and access statistics, lowering the refresh frequency by more than 5×, as compared to traditional worst-case design.

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Section: B Replica Technique Conceptmentioning

confidence: 85%

Section: Replica Technique For Auto-refresh Timing a Retention Tmentioning

confidence: 99%

Section: Replica Technique Integration Into Gain Cell Arraymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

Teman

Meinerzhagen

Giterman

et al. 2014

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

show abstract

“…The gain cells using three or more devices [3][4][5][6][7] may increase the data retention, but they carry considerable bit-area penalty. The gain cell in a hybrid structure of PMOS and NMOS [8] also consumes a spacious bit-area because of large well-towell space.…”

Section: Introductionmentioning

confidence: 99%

A Logic-compatible Embedded DRAM Utilizing Common-body Toggled Capacitive Cross-talk

Cheng¹,

Das²,

Chung³

2016

JSTS:Journal of Semiconductor Technology and Science

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2D Atomic Crystals: A Promising Solution for Next‐Generation Data Storage

Hou

Chen

Zhang

et al. 2019

Adv Elect Materials

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With the rapid development of the information age, more and more new technologies such as big data and cloud computing are beginning to emerge. As a result, the demand for high data‐storage density is becoming more and more urgent. In the past 10 years, data‐storage density has been greatly improved by reducing the size of memory cells. However, as semiconductor technology nodes have shrunk, a number of problems have appeared in metal–oxide–semiconductor field‐effect transistor (MOSFET)‐based memory cells, such as gate‐induced drain leakage, drain‐induced barrier lowering, and reliability issues. Fortunately, due to their atomic thickness, high mobility, and sustainable miniaturization properties, 2D atomic crystals (2D materials) are considered the most promising substitute for silicon to solve those issues. This review investigates the use of 2D materials in nonvolatile and volatile memories, including MOSFET‐based memory, magnetic random‐access memory, resistive random‐access memory, dynamic random‐access memory, semi‐floating‐gate memory, and other novel memories.

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A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor

Cited by 37 publications

References 14 publications

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

A Logic-compatible Embedded DRAM Utilizing Common-body Toggled Capacitive Cross-talk

2D Atomic Crystals: A Promising Solution for Next‐Generation Data Storage

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