A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology

Singh, A.P.; Ciraula, Michael; Weiss, D.; Wuu, John; Bauser, Philippe; Champs, Paul de; Daghighian, Hamid; Fisch, David; Graber, P.; Bron, Michel

doi:10.1109/isscc.2009.4977507

Cited by 10 publications

(3 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this paper, we propose and validate via numerical simulations, a new device that exploits TPA and the floating body effect in a metal-insulator-silicon (MOS) transistor on SOI substrate. In our device, the floating body effect [4,5] is exploited to create a large gain during conversion of 1550 nm wavelength photons to electrical current (or voltage). Conventional phototransistors are based on bipolar junction transistors that also offer large internal gain.…”

Section: Introductionmentioning

confidence: 99%

Floating body CMOS phototransistor memory

Kishima

Hon

Jalali

2010

IEICE Electron. Express

View full text Add to dashboard Cite

An optoelectronic CMOS memory technology is proposed where photon induced floating body effect stimulates switching and hysteresis in the transistor. The floating body effect is induced by exceedingly few carriers generated by two photon absorption. In this paper we present the structure of proposing device and numerically validated the device by Atlas device simulator from SILVACO Corporation. Keywords: detectors, optical memories, integrated optics Classification: Optoelectronics, Lasers and quantum electronics, Ultrafast optics, Silicon photonics, Planar lightwave circuits References[1] H. K. Tsang, C. W. Wong, T. K. Lang, I. E. Day, S. W. Robert, A. Harpin, J. Drake, and M. Asghari, "Optical dispersion, two-photon absorption and self-phase modulation in silicon waveguides at 1.5 μm wavelength," Appl.

show abstract

Section: Introductionmentioning

confidence: 99%

Floating body CMOS phototransistor memory

Kishima

Hon

Jalali

2010

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…For these advantages, bulk FinFETs have been chosen for our experiments. Although the principle of FB-RAM has been proven at the device level in different technologies and for different device architectures, few efforts targeting full memory implementations have been reported to date [13]. The first design challenge relates to the choice of the bias conditions for the READ, WRITE "1/0," and HOLD operations.…”

Section: Introductionmentioning

confidence: 99%

Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM

Poliakov

Anchlia

Bardon

et al. 2010

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

Single-transistor floating-body RAM (FB-RAM) cells present a promising alternative for scalable high-density storage since both access and storage elements are implemented using a single FET-based device. Unlike embedded dynamic RAM (eDRAM) technology, the concept is fully scalable with decreasing technology nodes. However, to make the concept truly usable, special biasing conditions of the device need to be considered; hence, the peripheral elements must be designed accordingly. We propose an approach of FinFET-based cell and peripheral circuit to provide compatible bias conditions for efficient write-read and hold conditions. The periphery is based on the synchronized bit line and word line driver schemes capable of providing compatible voltages to the selected and unselected lines during the different operations. The full circuit has been validated, and the concept has been demonstrated by simulations using the silicon-proven model cards and design decks. Index Terms-BulkFinFET, capacitorless dynamic RAM (DRAM), floating-body RAM (FB-RAM), single-transistor cell memory.

show abstract

“…Although the principle of the FB-RAM has been proven at device level in different technologies and for different device architectures, few efforts targeting the full memory implementations have been reported to date [8]. Different challenges arise when designing a FB-RAM memory array.…”

Section: Introductionmentioning

confidence: 99%

Circuit Design for Bias Compatibility Investigation of Bulk FinFET Based Floating Body RAM

Anchlia

Bardon

Poliakov

et al. 2009

2009 IEEE International Workshop on Memory Technology, Design, and Testing

View full text Add to dashboard Cite

Single transistor Floating Body Random Access Memories (FB-RAMs) are foreseen to bring size and speed benefits and have the potential to replace existing DRAMs. However, the implementation in matrix is complex because the voltages applied to access one cell can disturb the state of other cells. We propose an approach at circuit level to provide compatible bias conditions and to explore further on the optimization of the biasing voltages for improved write and read operations and improved retention. To do so we use synchronized bitline and wordline drivers providing different voltages to selected and unselected lines during the different operations. In addition, a robust sensing scheme is described that can be implemented in the same process technology as the array. The full circuit has been validated by simulations based on the experimental data of fabricated bulk FinFETs floating body cells and the design has been taped out.

show abstract

A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology

Cited by 10 publications

References 5 publications

Floating body CMOS phototransistor memory

Floating body CMOS phototransistor memory

Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM

Circuit Design for Bias Compatibility Investigation of Bulk FinFET Based Floating Body RAM

Contact Info

Product

Resources

About