A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure

Yamagata, T.; Mihara, M.; Hamamoto, T.; Murai, Y.; Kobayashi, Toshifumi; Yamada, Michihiro; Ozaki, H.

doi:10.1109/4.173123

Cited by 46 publications

(7 citation statements)

References 17 publications

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“…Data aware proposed TCAM cell is shown in Figure 1, which consists of a data aware block to reduce the redundant computation word bit line WBL and its complement address select line SBL and a discharge transistor N6 [12] [13].…”

Section: Proposed Designs 21 Proposed Data Aware Tcam (Datcam)mentioning

confidence: 99%

Data Intelligent Low Power High Performance TCAM for IP-Address Lookup Table

Mathan¹,

Ravichandran²

2016

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This paper represents current research in low-power Very Large Scale Integration (VLSI) domain. Nowadays low power has become more sought research topic in electronic industry. Power dissipation is the most important area while designing the VLSI chip. Today almost all of the high speed switching devices include the Ternary Content Addressable Memory (TCAM) as one of the most important features. When a device consumes less power that becomes reliable and it would work with more efficiency. Complementary Metal Oxide Semiconductor (CMOS) technology is best known for low power consumption devices. This paper aims at designing a router application device which consumes less power and works more efficiently. Various strategies, methodologies and power management techniques for low power circuits and systems are discussed in this research. From this research the challenges could be developed that might be met while designing low power high performance circuit. This work aims at developing Data Aware AND-type match line architecture for TCAM. A TCAM macro of 256 × 128 was designed using Cadence Advanced Development Environment (ADE) with 90 nm technology file from Taiwan Semiconductor Manufacturing Company (TSMC). The result shows that the proposed Data Aware architecture provides around 35% speed and 45% power improvement over existing architecture.

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Section: Proposed Designs 21 Proposed Data Aware Tcam (Datcam)mentioning

confidence: 99%

Data Intelligent Low Power High Performance TCAM for IP-Address Lookup Table

Mathan¹,

Ravichandran²

2016

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“…Notable exceptions to the static CAM schema are dynamic implementations of the core cell [25]- [28]. They are more complex than those of a typical high-density dynamic RAM, due to the necessity of charge retention during the simultaneous data comparison process.…”

Section: Content-addressable Memoriesmentioning

confidence: 99%

A framework for testing special-purpose memories

Sidorowicz¹,

Brzozowski

2002

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Current memory testing methods rely on fault models that are inadequate to accurately represent potential defects that occur in modern, often specialized, memories. To remedy this, the authors present a formal framework for modeling and testing special-purpose memories. Their approach uses three models: the transistor circuit, the event-sequence model, and finite-state machines. The methodology is explained using the example of a content-addressable memory (CAM). The fault model they describe comprises input stuck-at, transistor, and bridging faults. The authors show that functional tests can reliably detect all input stuck-at faults, most transistor faults (including all stuck-open faults), and about 50% of bridging faults. The remaining faults are detectable by parametric tests. A test of length 7 + 2 + 9 that detects all the reliably testable faults in an-word by-bit CAM is presented. A CAM test by Giles & Hunter is evaluated with respect to the input stuck-at faults. It is shown that this test fails to detect certain faults; it can be modified to achieve full coverage at the cost of increased length.

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“…Figures 6 and 7 show the one-word circuits of a binary dynamic CAM [7] and a digit-serial multiple-valued CAM [5], respectively. Table 2 summarizes the comparison of CAMs whose word length is 8 bits.…”

Section: Performance Evaluationmentioning

confidence: 99%

“…Finally, in an HSPICE simulation, under a 0.8-mm standard EEPROM design rule, the performance of the proposed digit-parallel multiple-valued CAM is evaluated in comparison with that of a conventional binary CAM [7] and that of a digit-serial multiple-valued CAM [5]. It is shown that the execution time and power dissipation of the proposed digit-parallel 4-valued CAM with an 8-bit word can be greatly reduced in comparison with those of other corresponding CAMs.…”

Section: Introductionmentioning

confidence: 99%