A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme

Abstract

This paper presents a low-energy 64-Kb 8-transistor (8T) one-read/one-write dual-port image memory with a 28-nm fully depleted SOI (FD-SOI) process technology. Our proposed SRAM adopts a selective sourceline drive (SSD) scheme and a consecutive data write technique for improving active energy efficiency at low voltage. The novel SSD scheme controls sourceline voltage and eliminates leakage energy at unselected columns in read operations. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology. The 8T SRAM cell size is 0.291 × 1.457 µm 2 . The test chip exhibits 0.48-V operation at access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operations and 389.6 fJ/cycle in read operations are achieved. These factors are, respectively, 30% and 26% smaller than those of the 8T dual-port SRAM with the conventional scheme.

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

“…17 shows the layout of the Nwise and Pwise cells, respectively. All the memory cells are implemented with regular threshold voltage (RVT) transistors [65], [66] in order to minimize leakage current. The RVT transistors are implemented in the layout with conventional well, i.e., N-channel devices reside in P-well and P-channel devices in N-well.…”

An Ultra-Low Leakage Bitcell Structure with the Feedforward Self-Suppression Scheme for Near-Threshold SRAM

“…Although seven-(7T) and eight-transistor (8T) single-ended bitcells [2], [3] are proposed, their leakage power cannot be decreased rapidly along with VDD in contrast to the dynamic power. Worse still, the extra read port would introduce more leaking paths with higher leakage power consumption [4].…”