A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro

Song, Jiahao; Tang, Xiyuan; Qiao, Xin; Wang, Yuan; Wang, Runsheng; Huang, Ru

doi:10.1109/tcsi.2023.3244338

Cited by 13 publications

(4 citation statements)

References 43 publications

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“…Previously, silicon-based SNNs, such as TrueNorth, demonstrated a large-scale neuromorphic computing system, where transposable static random access memory (SRAM) was used as a single synaptic cell. [11][12][13][14][15][16][17] The transposable SRAMs guarantee relatively high uniformity and reliability and are fabricated using mature conventional complementary metal-oxide-semiconductor (CMOS) fabrication technology. [17][18][19] Moreover, in SRAM-based SNNs, STDP can be implemented using stochastic learning rules with binarized synaptic weights.…”

Section: Introductionmentioning

confidence: 99%

“…[11][12][13][14][15][16][17] The transposable SRAMs guarantee relatively high uniformity and reliability and are fabricated using mature conventional complementary metal-oxide-semiconductor (CMOS) fabrication technology. [17][18][19] Moreover, in SRAM-based SNNs, STDP can be implemented using stochastic learning rules with binarized synaptic weights. [15,20] However, transposable SRAMs require at least six transistors per synaptic cell.…”

Section: Introductionmentioning

confidence: 99%

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Bidirectional Synaptic Operations of Triple‐Gated Silicon Nanosheet Transistors with Reconfigurable Memory Characteristics

Shin,

Son,

Jeon

et al. 2024

Adv Elect Materials

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In this study, a triple‐gated transistor with a p+‐i‐n+ silicon nanosheet (NS) is proposed as a single synaptic device, and bidirectional synaptic functions are realized using reconfigurable memory characteristics. The triple‐gated NS transistor features steep switching and bistable characteristics with a subthreshold swing below 5 mV dec−1 and an ON/OFF current ratio of ≈5 × 106 for both the n‐ and p‐channel modes. This transistor exhibits electrically symmetric reconfigurable memory characteristics with an ON current ratio of 1.02 for the n‐ and p‐channel modes. Moreover, the bidirectional synaptic weight updates of binarized spike‐timing‐dependent plasticity learning are successfully performed in a single transistor. This study demonstrates the potential of a triple‐gated NS transistor for achieving compact synaptic arrays in large‐scale silicon‐based neuromorphic computing systems.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Bidirectional Synaptic Operations of Triple‐Gated Silicon Nanosheet Transistors with Reconfigurable Memory Characteristics

Shin,

Son,

Jeon

et al. 2024

Adv Elect Materials

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“…Therefore, static random access memory (SRAM), which can read/write at high speed, is the best choice for implementing an IMC structure. In addition, unlike dynamic Recently, the SRAM-IMC of charge-domain computing has been reported to address the limitations of current-domain computing [17][18][19][20][21][22][23][24][25][26][27]. As shown in Figure 1, charge-domain computing uses capacitors added inside individual bitcells to perform analog multiplication.…”

Section: Introductionmentioning

confidence: 99%

“…Figure 2d,e provide an overview of charge-domain bitcells. Although 10T1C bitcells [25] achieve high linearity in large arrays, they occupy a substantial individual cell Recently, the SRAM-IMC of charge-domain computing has been reported to address the limitations of current-domain computing [17][18][19][20][21][22][23][24][25][26][27]. As shown in Figure 1, charge-domain computing uses capacitors added inside individual bitcells to perform analog multiplication.…”

Section: Introductionmentioning

confidence: 99%

Charge-Domain Static Random Access Memory-Based In-Memory Computing with Low-Cost Multiply-and-Accumulate Operation and Energy-Efficient 7-Bit Hybrid Analog-to-Digital Converter

Lee,

Kim

2024

Electronics

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This study presents a charge-domain SRAM-based in-memory computing (IMC) architecture. The multiply-and-accumulate (MAC) operation in the IMC structure is divided into current- and charge-domain methods. Current-domain IMC has high-power consumption and poor linearity. Charge-domain IMC has reduced variability compared with current-domain IMCs, achieving higher linearity and enabling energy-efficient operation with fewer dynamic current paths. The proposed IMC structure uses a 9T1C bitcell considering the trade-off between the bitcell area and the threshold voltage drop by an NMOS access transistor. We propose an energy-efficient summation mechanism for 4-bit weight rows to perform energy-efficient MAC operations. The generated MAC value is finally returned as a digital value through an analog-to-digital converter (ADC), whose performance is one of the critical components in the overall system. The proposed flash-successive approximation register (SAR) ADC is designed by combining the advantages of flash ADC and SAR ADC and outputs digital values at approximately half the cycle of SAR ADC. The proposed charge-domain IMC is designed and simulated in a 65 nm CMOS process. It achieves 102.4 GOPS throughput and 33.6 TOPS/W energy efficiency at array size of 1 Kb.

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In-memory computing: characteristics, spintronics, and neural network applications insights

Jangra,

Duhan

2024

Multiscale and Multidiscip. Model. Exp. and Des.

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A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro

Cited by 13 publications

References 43 publications

Bidirectional Synaptic Operations of Triple‐Gated Silicon Nanosheet Transistors with Reconfigurable Memory Characteristics

Bidirectional Synaptic Operations of Triple‐Gated Silicon Nanosheet Transistors with Reconfigurable Memory Characteristics

Charge-Domain Static Random Access Memory-Based In-Memory Computing with Low-Cost Multiply-and-Accumulate Operation and Energy-Efficient 7-Bit Hybrid Analog-to-Digital Converter

In-memory computing: characteristics, spintronics, and neural network applications insights

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