A 28-GHz, -187.4-dBc/Hz-FOM&lt;sub&gt;T&lt;/sub&gt; Low-Phase-Noise CMOS VCO Using an Amplitude-Redistribution Technique

Wachi, Yusuke; Nagasaku, Toshiyuki; Kondoh, Hiroshi

doi:10.1587/transele.e95.c.1042

Cited by 9 publications

(16 citation statements)

References 9 publications

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“…The oscillation amplitude in this VCO is limited by the nonlinearity of the large-signal device transconductance . 1 To provide some intuition regarding the key drivers of the phase noise performance, we plot the effective large-signal transconductance versus gate ac swing for the cross-coupled VCO in Curve I in Fig. 2.…”

Section: Transconductance Linearizationmentioning

confidence: 99%

“…Note that this determines the active device noise power at the oscillation zero 1 Here, is defined as , where and are the ac drain current and ac gate voltage at the frequency of oscillation . crossings (when the oscillator's phase noise sensitivity is at its highest).…”

Section: Transconductance Linearizationmentioning

confidence: 99%

“…Using these novel approaches, we are able to optimize the VCO for phase noise, power, and tuning range. Consequently, the implemented PLL incorporating the resulting linear transconductance VCO (LiT VCO) achieves both an excellent measured phase noise of 130 dBc/Hz at 22 GHz (10-MHz offset), and, in contrast to the 6.7% tuning range of the VCO-only result reported using a somewhat similar technique in [1], a large frequency tuning range (FTR) of 23% (21.8-27.5 GHz). This range covers operation over 22.…”

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confidence: 99%

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A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

Sadhu

Ferriss

Natarajan

et al. 2013

IEEE J. Solid-State Circuits

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Abstract-This paper describes a new approach to low-phasenoise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is 0.6 dB. Also, phase noise variation across supply voltages of 0.7-1.5 V is 2 dB and across 60 temperature variation is 3 dB. At the 25 GHz center frequency, the VCO is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme.

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Section: Transconductance Linearizationmentioning

confidence: 99%

Section: Transconductance Linearizationmentioning

confidence: 99%

mentioning

confidence: 99%

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A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

Sadhu

Ferriss

Natarajan

et al. 2013

IEEE J. Solid-State Circuits

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“…6(c), the associated transistors and forms an equivalently negative , and the circuit oscillates at the higher frequency peak. Making use of the transformer, the gate voltages and drain voltages of can be independently biased to redistribute the amplitudes and keep the transistors from entering into triode region [25]. Interestingly, the topology of the two-port oscillator is very similar to the Class-C oscillator as proposed in [26], and the phase noise can be expressed as: (16) where C is the differential capacitance at the transistor's gate, which is equal for the low band or for the highband, is the transistor noise factor close to 2/3, and is the voltage ratio of the gate amplitude to the drain amplitude.…”

Section: Tank Quality Factors-qsmentioning

confidence: 99%

Analysis and Design of Transformer-Based Dual-Band VCO for Software-Defined Radios

Rong

Luong

2012

IEEE Trans. Circuits Syst. I

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This work presents complete analysis of both oneport and two-port dual-band oscillators using transformer-based fourth-order LC tanks, from which critical parameters including oscillation frequency, start-up condition, tank Q, phase noise-are thoroughly derived and compared. It is shown that one-port oscillators consume less power than two-port counterparts but may suffer from stability problem which can be solved by a notch-peak cancellation technique. On the other hand, compared to one-port oscillators, two-port oscillators need to consume more power to obtain the same output swing, but their phase noise can be improved more linearly with increasing bias current, and thus they can achieve lower phase noise with a sufficiently large bias current. Based on the results, a dual-band quadrature voltage-controlled oscillator (Q-VCO) is systematically designed and implemented in a 0.13-m CMOS process for software-defined -radio (SDR) applications, in which the two-port topology is used in the low band for low phase noise and the one-port topology is employed in the high band for low power consumption. The prototype achieves a dual-band operation with in-phase and quadrature-phase (IQ) output signals from 2.7 GHz to 4.3 GHz and from 8.4 GHz to 12.4 GHz. At 3.6 GHz and 10.4 GHz, phase noise at 3 MHz offset of dBc/Hz and dBc/Hz and sideband-rejection ratios (SBR) of 37 dB and 41 dB are measured, respectively.

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“…For synthesizer applications, an integrated FOM parameter may be important for a given application. From (12) and (13), the FOM for integrated phase noise in dBc from 1 kHz to 1 MHz is given by [1] A resonator of high Q implies low loss, thereby providing the capability to lower the phase noise of the oscillators. The novel X-band oscillator proposed here allows for the design of an oscillator with state-of-the-art phase-noise performance, close to the phase noise of expensive, high-Q-factor dielectric resonator oscillators (shown in Table 1), while providing a compact and planar structure compatible with hybrid and integrated circuit fabrication technologies.…”

Section: Design Criteria (Ims2014 Sdc)mentioning

confidence: 99%