A 28 GHz 0.18-μm CMOS cascade power amplifier with reverse body bias technique

Abstract

A 28 GHz power amplifier (PA) using CMOS 0.18 µm Silterra process technology is reported. The cascade configuration has been adopted to obtain high Power Added Efficiency (PAE). To achieve low power consumption, the input stage adopts reverse body bias technique. The simulation results show that the proposed PA consumes 32.03mW and power gain (S21) of 9.51 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 11.10 dBm and maximum PAE of 16.55% with output 1-dB compression point (OP1dB) 8.44 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.

A 28 GHz high efficiency fully integrated 0.18 µm combined CMOS power amplifier using power divider technique for 5G millimeter-wave applications

“…The design with the three-stage of cascaded amplification is chosen to achieve the required gain. The output stage is designed to provide maximum output power while the first and second stages are designed for maximum gain.Power gain of the cascade system increase due to current and voltage gain increased by cascading the amplifier stage [25]. Therefore, the need for cascading is important to maintain the power gain.…”