A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS

Kimura, Hiroshi; Aziz, P.M.; Jing, Tai; Sinha, Ashutosh Kumar; Narayan, Ram; Gao, Hairong; Jing, Ping; Hom, Gary; Liang, Anshi; Zhang, Eric; Kadkol, Aniket; Kothari, Ruchi; Chan, Gordon; Sun, Yehui; Ge, Benjamin; Zeng, Jason; Ling, Kathy; Wang, Michael; Malipatil, Amaresh; Kotagiri, Shiva Prasad; Li, Lijun; Abel, Chris; Zhong, Freeman

doi:10.1109/jssc.2014.2349974

Cited by 75 publications

(22 citation statements)

References 18 publications

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“…While it is possible to achieve a comparable bandwidth using high-speed SERDES MGTs (multi-gigabit transceivers) [Kimura et al 2014], the very high bandwidth consumes significant power to drive the high capacitance chip-tochip and board-to-board connectors [Hasler and Marr 2013] and to maintain synchronization. Using Kimura et al [2014], in which 28Gbps is achieved with 560mW in a 28nm technology, we estimate an added 4W per node just for the high bandwidth communications, resulting in an added 400kW for a human scale system. Each SERDES operation also adds a delay of ∼100ns for serialization and deserialization to the time for each hop.…”

Section: Discussionmentioning

confidence: 99%

Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration

Kumar

Wan

Wilcke

et al. 2017

J. Emerg. Technol. Comput. Syst.

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The Von Neumann architecture, defined by strict and hierarchical separation of memory and processor, has been a hallmark of conventional computer design since the 1940s. It is becoming increasingly unsuitable for cognitive applications, which require massive parallel processing of highly interdependent data. Inspired by the brain, we propose a significantly different architecture characterized by a large number of highly interconnected simple processors intertwined with very large amounts of low-latency memory. We contend that this memory-centric architecture can be realized using 3D wafer scale integration for which the technology is nearing readiness, combined with current CMOS device technologies. The natural fault tolerance and lower power requirements of neuromorphic processing make 3D wafer stacking particularly attractive. In order to assess the performance of this architecture, we propose a specific embodiment of a neuronal system using 3D wafer scale integration; formulate a simple model of brain connectivity including short-and long-range connections; and estimate the memory, bandwidth, latency, and power requirements of the system using the connectivity model. We find that 3D wafer scale integration, combined with technologies nearing readiness, offers the potential for scaleup to a primate-scale brain, while further scaleup to a human-scale brain would require significant additional innovations.

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Section: Discussionmentioning

confidence: 99%

Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration

Kumar

Wan

Wilcke

et al. 2017

J. Emerg. Technol. Comput. Syst.

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“…First, the gain of the multiplexer is increased by both the inductive peaking and current blocking technique, resulting in reducing the T d,mux1 to T s,mux1 . Second, we adopt a strong-arm latch [7] instead of a conventional current mode logic (CML) latch to improve the latch gain, As a result, the reduced latch delay decreases the critical path delay constraints approximately equation (1). In addition, the proposed latch reduces the transition time by half of the input data transition, which leads to dynamic power reduction because the evaluation rate of latch is 1/2 of data rate.…”

Section: B 2-tap Speculative Dfe With 4-phase Clockingmentioning

confidence: 99%

“…Since the equalizer is a dominant power consuming block to cancel the ISI caused by frequencydependent channel losses such as skin effect and dielectric loss, it is very important to reduce the power consumption of the equalizer in the recent high data rate wireline receivers. The previous receivers for over 28-Gb/s data rate [1]- [3] consume huge power larger than 100 mW, because they integrated many taps (up to 15) to cancel the long-term residual ISI. Since the large number of decision feedback equalizer (DFE) taps proportionally increases the number of the required DFE slicers or latches, which consuming huge power and area.…”

Section: Introductionmentioning

confidence: 99%

A 24-mW 28-Gb/s wireline receiver with low-frequency equalizing CTLE and 2-tap speculative DFE

Kim

Bae

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper, a power-efficient equalization techniques is proposed for a high data-rate multi-standard wireline receiver. First, a low-frequency-equalizing continuoustime linear equalizer (LFE-CTLE) compensates for not only the short-term inter-symbol interference (ISI) from high-frequency channel loss but also the long-term ISI from the low-frequency channel loss without additional power consumption compared to the previous CTLE. LFE-CTLE can reduce the required number of taps and power consumption of the following decision feedback equalizer (DFE). A 2-tap speculative DFE adopts 4-phase clocking techniques to reduce the number of summation nodes and latches for low-power consumption. The proposed receiver is designed in 65-nm LP CMOS technology with 1.-2V supply voltage. It can achieve 28-Gb/s data rate with a 24-mW power efficiency.Keywords-Continuous-time linear equalizer (CTLE), decision feedback equalizer (DFE), equalizer, intersymbol interference (ISI), low frequency equalizer (LFEQ), unrolled DFE, speculative DFE

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“…This is reflected in the growing capabilities and capacities of internal components and, consequently, the interconnects linking those elements. Currently, most state-of-the-art transceivers apply single-input singleoutput (SISO) decision-feedback equalization (DFE) or Tomlinson-Hirashima precoding (THP), to deal with the inter symbol interference (ISI) caused by highfrequency attenuation [1], [2]. In addition, various techniques have been proposed to mitigate crosstalk (XT) from adjacent conductors [3]- [5].…”

Section: Introductionmentioning

confidence: 99%

MIMO Equalization for Multi-Gbit/s Access Nodes Affected by Manufacturing Tolerances

Jacobs

Bailleul

Manfredi

et al. 2017

GLOBECOM 2017 - 2017 IEEE Global Communications Conference

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Abstract-While the requirements for delivering high throughputs increase exponentially with every generation of access node hardware, the device cost is of primary concern. As a result, multiple-input multipleoutput (MIMO) equalization, which has been shown to facilitate multi-Gbit/s communication over low-cost parallel electrical interconnects, is emerging as an attractive high-speed interconnect solution for next-generation access nodes. Because of the high operating frequencies, however, the transfer functions of the on-and off-chip interconnects become highly susceptible to manufacturing tolerances (MTs); hence, the equalization filters must be adjusted to the specific channel realization to achieve optimal performance, which involves a high implementation and computational complexity. Considering that the MTs are usually limited, we propose a robust lowcomplexity transceiver consisting of a fixed MIMO linear pre-equalizer (which avoids the need for feeding back the channel state information to the transmitter), with either a fixed or adjustable MIMO decision-feedback equalizer (DFE). For a specific chip-to-chip interconnect operating at 75 Gbit/s per line and a 26 dB signal-to-noise ratio, we show that the resulting bit error rate does not exceed 10 −12 for MTs up to 10.5% (fixed DFE) and 17.7% (adjustable DFE) of the nominal line width.

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A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS

Cited by 75 publications

References 18 publications

Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration

Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration

A 24-mW 28-Gb/s wireline receiver with low-frequency equalizing CTLE and 2-tap speculative DFE

MIMO Equalization for Multi-Gbit/s Access Nodes Affected by Manufacturing Tolerances

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