A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines

A design method of CPR for wide voltage design

“…The existing CPR design methods mainly include inverter line [13,21,22], mixed-gate CPR [23,24] and UDL (Universal Delay Line) [25]. The inverter line is the most commonly used CPR and its design is simple [26,27].…”

Mitigating Silent Data Corruptions in Integer Matrix Products: Toward Reliable Multimedia Computing on Unreliable Hardware

“…We present an example of the efficacy of our proposal as a power saving technique within systems where it is imperative to ensure reliable performance at reduced energy consumption. Voltage scaling is commonly found today within poweraware computing for multimedia systems [26]. Recently, voltage overscaling…”

A Survey on Low-Power Techniques for Single and Multicore Systems

“…Generic performance monitors range from simple inverterbased ring oscillators [29] to more complex process-specific ring oscillators (RO) [30] and also alternative monitoring Power reduction Comments [6] II.A Encoding FSM & decomposition to sub-FSMs 30% to 90% 20% to 120% area overhead [7] II.A Splitting memory into smaller sub-systems 75% sub-banking, bit-line segmentation, multiple-line buffers -no performance overhead [8] II.A DPTC 38.5% 1.8% performance overhead over CTC [9] II.A Drowsy cache 53% 4.06% to 12.46% performance overhead [10] II.A Adaptive instruction queue 70% Complexity of additional circuitry is negligible [5] II.A Clock gating up to 40% small area overhead [11] II.A Transistor sizing up to 15.3% 20% of transistors are resized [14] II.A Transistor reordering 18% minimum area overhead, no performance overhead [12] II.A Half-swing clock 67%-75% small speed degradation [16] II.B Bus inversion 50%-25% peak and average power reduction of I/O [17] II.B Low swing bus 62% to 78% 45% performance overhead [21] II.B Bus segmentation 24.6% to 37.21% 6% area overhead [22] II.B Adiabatic bus 28% - [26] III.A Three domain DVFS 65% power overhead: 9.5%, area overhead: 2.6% compared to single domain [27] III.A UDFS-PDVS 50% to 75% compared to Windows XP DVFS [33] III.A Universal delay line 13% to 27% area overhead: 0.01%, power overhead is negligible [23] III.A In-situ delay monitoring (over-critical) 13.5% compared to the worst-case design, prediction error rate: 1.10 −15 [32] III.A In-situ delay monitoring (regular) 14% power overhead: 0.5%, area overhead: 10% [34] III.A Critical path replica 11% to 78% highly dependent on the benchmark [36] III.A RCP 31% smaller guard-band than critical path replica, prediction error rate: 2.8% structure such as PLLs [31]. Although generic monitors are very simple to design and can be used in any product without customizations, they are inadequate to capture design characteristics, and there will be a large error in the measurements due to the difference in gate structure between the actual critical path and the delay monitor.…”

“…So, delay estimation using generic monitors is less accurate and sometimes incurs larger margins. However, the generic performance monitor proposed in [33] tries to minimize the errors due to gate structure difference by utilizing certain chain of delay gates, as well as the errors due to the within die variations by distributing monitors among the chip. Each performance monitor, which is called a universal delay line, contains a ring oscillator and a counter.…”