A 27‐33 <scp>GHz</scp> compact medium power amplifier with pole‐tuning technique in 130 nm <scp>CMOS</scp> technology

Qian, Xing; Luo, Jian

doi:10.1002/mop.32590

Cited by 3 publications

(4 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This work Chen et al 22 Quan and Luo 23 Chen et al 24 Lee et al F I G U R E 2 5 (A) Saturated output power, O1dB, and maximum power gain and (B) drain efficiency (%), and power added efficiency (PAE) (%) simulation results of the suggested power combiner over the frequency band connection lines) were designed and simulated using Ansoft high-frequency structure simulator (HFSS) to ensure accurate results. The three stages of the proposed PA operate in class-C, class-AB, and class-AB, respectively, by controlling the biasing voltage of the input, driver, and output stages of the suggested PA.…”

Section: Indexmentioning

confidence: 77%

“…A 130 nm mm‐wave CMOS power amplifier (PA) has been fabricated in Chen et al 22 It consumes, nevertheless, a big die size of 0.75 mm 2 and covers a single frequency band at 26 GHz, and the DC power consumption does not mention in the paper. In Quan and Luo, 23 a 27–33 GHz pole‐tuning power amplifier was presented with low output 1 dB compression point of 4.4–7.2 dBm over the frequency band, and the efficiency does not report in the paper. A transformer‐coupled power amplifier was proposed in Chen et al, 24 and it draws a current of 90 mA from 1.2 V supply voltage and achieves a low PAE of 8.4%.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

Mansour

2022

Circuit Theory & Apps

View full text Add to dashboard Cite

High‐efficiency and high‐linearity three‐stage transformer‐coupled power amplifier (PA) and power combiner for millimeter‐wave applications using 130 nm CMOS technology are presented in the paper. The suggested PA uses transformer coupled for input, inter‐stage, and output matching networks where the inter‐stage matching inductors are utilized to enhance the RF performance. The proposed power amplifier is composed of three stages: first, driver, and power stages. The first stage operates in a class‐C to improve the efficiency and decrease power dissipated while a class‐AB is used in the driver and power stages to maximize the output power. The proposed PA and power combiner designs are suitable for mm‐wave 5G applications. The coupling transformers, inter‐stage matching inductors, and output combiner are analyzed and designed using Ansoft high‐frequency structure simulator (HFSS) and achieve high‐quality factor and high‐coupling coefficient over the frequency range from 26 to 33 GHz. The proposed three‐stage transformer‐coupled power amplifier covers a frequency band from 26 GHz to 33 GHz with a saturated output power of 13.1 dBm, a peak power added efficiency (PAE) equals 19.1%, and a maximum power gain of 13.25 dB. Whereas the proposed power combiner has a saturated output power of 16.3 dBm, a maximum PAE equals 20.5% and a peak gain of 16.5 dB. The proposed three‐stage transformer‐coupled PA and power combiner consume low power of 65 mW and 128 mW, respectively. Moreover, the adjacent channel power ratios (ACPR) of the proposed PA and power combiner equal −30 dBc and −36 dBc, respectively, for 20 MHz channel bandwidth. Finally, the active areas of the proposed power amplifier and power combiner equal 0.25 mm2 and 0.69 mm2, respectively, while the chip areas are 0.55 mm2 and 1 mm2, respectively.

show abstract

Section: Indexmentioning

confidence: 77%

Section: Introductionmentioning

confidence: 99%

Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

Mansour

2022

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…As new wireless applications are widely deployed from X-band to K-band, there is an urgent need to develop highly integrated and low-cost broadband amplifiers, which have been the focus of many related applications. [6][7][8][9][10][11][12] The low noise amplifier (LNA) is a crucial building block in the RF front-end systems, responsible for amplifying weak RF signals received from antennas while suppressing noise from subsequent stages to achieve an acceptable signal-to-noise ratio. Various new technologies have been used in recent years to enhance the bandwidth (BW) of LNA.…”

Section: Introductionmentioning

confidence: 99%

“…Wideband systems offer better scalability and potential compatibility with future wireless communication standards. As new wireless applications are widely deployed from X‐band to K‐band, there is an urgent need to develop highly integrated and low‐cost broadband amplifiers, which have been the focus of many related applications 6–12 …”

Section: Introductionmentioning

confidence: 99%

A compact 9–23 GHz low noise amplifier with bandwidth extension techniques in 0.18‐μm SiGe BiCMOS

Luo

Chen²

2023

Int J Numerical Modelling

Self Cite

View full text Add to dashboard Cite

In this paper, a novel wideband low noise amplifier (LNA) operating in the 9–23 GHz frequency range is presented. The proposed LNA design utilizes a combination technique consisting of pole‐tuning technique, shunt resistive‐capacitor negative feedback, and gate‐capacitive peaking technique to achieve significant bandwidth extension while maintaining acceptable overall performance. For verification, a one‐stage triple‐stacked LNA using the combination technique is designed and implemented in a 0.18‐μm SiGe BiCMOS heterojunction bipolar transistor (HBT) process. The fabricated prototype demonstrates a peak gain of 13.8 dB at 19.5 GHz, minimum noise figure of 3.1 dB at 14 GHz, 3‐dB bandwidth of 14 GHz, and a fractional bandwidth of 87.5%, while consuming a dc power of 39.6 mW. Moreover, the chip occupies a small silicon area of 0.39 mm2 including all testing pads with a core size of only 0.192 mm2.

show abstract

Comprehensive study of Class‐‐E/F₂ and inverse Class‐‐F power amplifiers for mm‐Wave systems utilizing 130 nm CMOS process

Mansour,

Mansour

2024

Circuit Theory & Apps

View full text Add to dashboard Cite

This paper presents a comprehensive study of Class‐‐E/F2 and inverse Class‐‐F power amplifiers (PAs) designed for 35–42 GHz millimeter‐wave applications, utilizing a 130 nm CMOS process. The proposed RF PAs are well suited for wide frequency‐band millimeter‐wave and 5G radio transmitters. A comprehensive study of limiting factors in amplifier efficiency is presented in this paper. The study encompasses an analysis of all the factors that restrict the efficiency of the switched power amplifier. The first proposed power amplifier is based on the Class E/F2 architecture, comprising a parallel capacitor, second harmonic resonance circuit, and output matching network. Conversely, the second suggested power amplifier is constructed using the inverse Class‐‐F topology, which includes harmonic termination and matching networks. The harmonic termination circuit incorporates a second harmonic resonance network and utilizes a parasitic capacitor to control the harmonic components. Both the proposed Class E/F2 and inverse Class‐‐F architectures are employed to reshape the drain current and voltage waveforms, aiming to reduce the overlap between them and, consequently, improve efficiency. The suggested power amplifiers comprise a driver Class‐‐AB stage and a power stage constructed based on either the Class E/F2 architecture or inverse Class‐‐F topology, utilizing harmonic termination networks at the output load. Two new designs of high‐Q factor on‐chip finger capacitors have been implemented to improve efficiency and radio frequency performance. Achieving input matching and inter‐stage matching is facilitated by employing two novel on‐chip transformers designed for maximum power transfer. Additionally, an inter‐stage matching inductor is utilized in a cascode configuration to enhance the overall RF performance. The on‐chip transformers, inductors, and finger capacitors are designed using the HFSS software program. S‐parameter files (SNP files) of the designed on‐chip components are extracted and inserted into the simulation tool to ensure accurate results. The proposed Class E/F2 power amplifier achieves a constant power of 14.9 dBm, an extreme power added efficiency (PAE) of 11.7%, and a maximum gain of 13.74 dB. In contrast, the suggested inverse Class‐‐F power amplifier attains a constant power of 15.4 dBm, a peak PAE of 12.6%, and a maximum gain of 14.8 dB. The DC power consumption is 73 and 66 mW for the proposed Class E/F2 and inverse Class‐‐F PAs, respectively, while their active sizes are 0.14 and 0.2 mm2.

show abstract

A 27‐33 GHz compact medium power amplifier with pole‐tuning technique in 130 nm CMOS technology

Cited by 3 publications

References 17 publications

Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

A compact 9–23 GHz low noise amplifier with bandwidth extension techniques in 0.18‐μm SiGe BiCMOS

Comprehensive study of Class‐‐E/F₂ and inverse Class‐‐F power amplifiers for mm‐Wave systems utilizing 130 nm CMOS process

Contact Info

Product

Resources

About

A 27‐33 GHz compact medium power amplifier with pole‐tuning technique in 130 nm CMOS technology

Cited by 3 publications

References 17 publications

Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

A compact 9–23 GHz low noise amplifier with bandwidth extension techniques in 0.18‐μm SiGe BiCMOS

Comprehensive study of Class‐‐E/F2 and inverse Class‐‐F power amplifiers for mm‐Wave systems utilizing 130 nm CMOS process

Contact Info

Product

Resources

About

Comprehensive study of Class‐‐E/F₂ and inverse Class‐‐F power amplifiers for mm‐Wave systems utilizing 130 nm CMOS process