A 25ns 4K static RAM

Jecmen, R.; Ebel, Alexander; Smith, Richard J.; Kynett, V.; Hui, Chi-Hung; Pashley, R.

doi:10.1109/isscc.1979.1155936

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1979

1981

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Cited by 20 publications

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“…Major technological advances in bulk NMOS have allowed this to occur. Depletion loads, device scaling and projection printing were utilized to achieve the 4K density (l), (2). Now a second layer of polysilicon has been added for RAM cell pullups and interconnect.…”

Section: Introductionmentioning

confidence: 99%

A high-performance MOS technology for 16K static RAM

Liu

Smith

Pashley

et al. 1979

1979 International Electron Devices Meeting

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A scaled double-poly MOS technology has been developed which features a static memory cell size of 1.5 mil2 with 4p design rules using conventional photolithographic techniques. The technology scales the gate oxide thickness to 4008 and polySi channel length to 2.11-1 with arsenic source-drain and self-aligned poly-poly via contact. Four different types of transistors are implemented to enhance circuit design versatility. Hot electron failures and soft errors do not limit the applicability of the technology.

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Section: Introductionmentioning

confidence: 99%