A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links

Li, Dan; Minoia, Gabriele; Repossi, Matteo; Baldi, Daniele; Ghilioni, Andrea; Temporiti, Enrico; Svelto, F.

doi:10.1109/iscas.2016.7539052

Cited by 10 publications

(8 citation statements)

References 5 publications

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“…Indeed, we can separate the noise and bandwidth goals and deal with them sequentially to break the transimpedance limit. In view that noise is usually much more difficult to solve while bandwidth compensation can be conveniently carried out, a noisefirst-bandwidth-second two-step approach has been proposed [9], [14].…”

Section: Type I Approach: Break Transimpedance Limitmentioning

confidence: 99%

“…Fig. 4(b) provides a possible implementation to realize 25 Gb/s TSFE using 65-nm CMOS under 1V supply voltage [9], [14]. The TIA stage utilizes the popular CMOS inverter as its amplifier where the n factor of TIA stage is set to be around 2, with an NMOS cascode to boost the amplifier gain needed for larger RF.…”

Section: Type I Approach: Break Transimpedance Limitmentioning

confidence: 99%

“…In a similar implementation [18], paired with a silicon photonic Ge photodiode, the TSFE achieves an input-referred noise current of 0.91 μArms under 16.1 GHz electrical bandwidth, which is even better than SiGe counterparts thanks to the small capacitance from the photodiode, as well as the 3D integrated co-design approach. After its first introduction in [9], [14], the Type-I approach has been widely used adopted, where the EQ realization can be either analog continuous time linear equalizer (CTLE) [19]- [22], or digital decision feedback equalizer (DFE) [23]- [27].…”

Section: Type I Approach: Break Transimpedance Limitmentioning

confidence: 99%

See 2 more Smart Citations

Overcoming the Transimpedance Limit: A Tutorial on Design of Low-Noise TIA

Maloberti

et al. 2022

IEEE Trans. Circuits Syst. II

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Noise is probably the single most important performance metric of the high-speed transimpedance amplifier (TIA), which directly sets the sensitivity of optical receiver. The transimpedance limit which dictates the maximum achievable transimpedance gain of the TIA also turns out to fundamentally limit the TIA noise performance. In this tutorial, we analyze and explore the circuit design approaches to overcome the transimpedance limit, the key to achieve low noise, with design examples, consideration and guidelines. Both approaches can overcome the transimpedance limit, forming an effective toolkit on the design of lownoise high-speed TIA for high-sensitive CMOS optical receiver in current and future applications.

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Section: Type I Approach: Break Transimpedance Limitmentioning

confidence: 99%

Section: Type I Approach: Break Transimpedance Limitmentioning

confidence: 99%

Section: Type I Approach: Break Transimpedance Limitmentioning

confidence: 99%

See 1 more Smart Citation

Overcoming the Transimpedance Limit: A Tutorial on Design of Low-Noise TIA

Maloberti

et al. 2022

IEEE Trans. Circuits Syst. II

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“…Therefore, the bandwidth can be improved by lower the input impedance of TIAs [21]. Consequently, a regulatedcascode (RGC) circuit [22,23,24,25] is widely used for a wideband TIA because it has a low-input impedance characteristic, and various modified RGC circuits are investigated [26,27]. For more reducing the input impedance, a CR-RGC TIA using a current-reuse (CR) technique [28] based on the RGC TIA has been proposed [16].…”

Section: Conventional Cr-rgc Tia Circuitmentioning

confidence: 99%

A wideband current-reuse-RGC TIA circuit with low-power consumption

Hida

Nakane

Mizuno

et al. 2019

IEICE Electron. Express

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This paper presents a new Gain-Adder (GA) circuit for Current-Reuse (CR)-RGC TIA. The proposed GA circuit employs one transistor alone to enhance bandwidth and decrease power consumption. The proposed CR-RGC TIA circuit is designed in a 65-nm CMOS technology. The simulation results confirmed that the proposed CR-RGC TIA circuit improves bandwidth by 83% and decreases the power consumption by 34% in comparison with the conventional one.

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“…The transimpedance amplifier (TIA) typically included in optical receiver designs largely determines the overall sensitivity, operation speed, linearity performance and power consumption of the receiver module [13][14][15][16][17]. A number of optical receivers co-integrated with TIAs have been reported in the literature, the realisations of which were based on various technology platforms, including 250-nm, 130 T [13][14][15][16][17][18][19][20][21][22]. Owing to the higher dynamic range and transition frequency of the BiCMOS technology [23][24], most of the high-speed demonstrations of TIA-integrated optical receivers to date have been realised in BiCMOS processes.…”

Section: Introductionmentioning

confidence: 99%

High-Speed DD Transmission Using a Silicon Receiver Co-Integrated With a 28-nm CMOS Gain-Tunable Fully-Differential TIA

Hong

Lacava

et al. 2021

J. Lightwave Technol.

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We report >100-Gb/s direct-detection (DD) transmission using an integrated silicon optical receiver, which comprised a fully-differential 28-nm complementary metal-oxide-semiconductor (CMOS) transimpedance amplifier (TIA) wire-bonded to a Silicon-Germanium (SiGe) balanced photodiode (PD). The fully-differential TIA architecture enabled significant bit-error-rate (BER) and signal-to-noise ratio improvements over a single-output TIA design when introducing it to the DD transmission. We experimentally validated its effectiveness in both back-to-back (B2B) and 2-km long standard single-mode fibre (SSMF) links using 50/100-Gb/s signals, including Nyquist on-off keying (OOK), Nyquist 4-ary pulse amplitude modulation (PAM4), uniformly-loaded DD optical orthogonal frequency division multiplexing (DDO-OFDM) and adaptively-loaded DDO-OFDM. Furthermore, we demonstrate that the integrated optical receiver was capable of balancing the trade-off between its electrical bandwidth and transimpedance gain by simply adjusting a voltage supply to the TIA. Without the need for optical amplification and while keeping the BERs below the 7% forward error correction limit, up to 173.22-Gb/s and 139.86-Gb/s adaptively-loaded DDO-OFDM transmission was achieved for B2B and 2-km transmission, respectively. The demonstrated results highlight the potential of the integrated silicon optical receiver, fabricated using the standard CMOS process for high-speed and short-reach optical interconnects.

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A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links

Cited by 10 publications

References 5 publications

Overcoming the Transimpedance Limit: A Tutorial on Design of Low-Noise TIA

Overcoming the Transimpedance Limit: A Tutorial on Design of Low-Noise TIA

A wideband current-reuse-RGC TIA circuit with low-power consumption

High-Speed DD Transmission Using a Silicon Receiver Co-Integrated With a 28-nm CMOS Gain-Tunable Fully-Differential TIA

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